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? 1999 microchip technology inc. preliminary ds30221a-page 1 devices included in this data sheet: microcontroller core features: ? high-performance risc cpu ? only 35 single word instructions to learn ? all single cycle instructions except for program branches which are two cycle ? operating speed: dc - 20 mhz clock input dc - 200 ns instruction cycle ? 2k x 14 words of flash program memory 128 x 8 bytes of data memory (ram) 64 x 8 bytes of eeprom data memory ? pinout compatible to the pic16c72a ? interrupt capability (up to 10 sources) ? eight level deep hardware stack ? direct, indirect and relative addressing modes ? power-on reset (por) ? power-up timer (pwrt) and oscillator start-up timer (ost) ? watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation ? programmable code-protection ? power saving sleep mode ? selectable oscillator options ? low-power, high-speed cmos flash/eeprom technology ? fully static design ? in-circuit serial programming ? (icsp) via two pins ? single 5v in-circuit serial programming capability ? in-circuit debugging via two pins ? processor read/write access to program memory ? wide operating voltage range: 2.0v to 5.5v ? high sink/source current: 25 ma ? commercial and industrial temperature ranges ? low-power consumption: - < 2 ma typical @ 5v, 4 mhz -20 m a typical @ 3v, 32 khz -< 1 m a typical standby current pin diagram peripheral features: ? timer0: 8-bit timer/counter with 8-bit prescaler ? timer1: 16-bit timer/counter with prescaler, can be incremented during sleep via external crystal/clock ? timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler ? one capture, compare, pwm module - capture is 16-bit, max. resolution is 12.5 ns - compare is 16-bit, max. resolution is 200 ns - pwm max. resolution is 10-bit ? 10-bit multi-channel analog-to-digital converter ? synchronous serial port (ssp) with spi ? (master mode) and i 2 c ? (master/slave) ? brown-out detection circuitry for brown-out reset (bor) ?pic16f872 pic16f872 10 11 2 3 4 5 6 1 8 7 9 12 13 14 15 16 17 18 19 20 23 24 25 26 27 28 22 21 mclr /v pp /thv ra0/an0 ra1/an1 ra2/an2/v ref - ra3/an3/v ref + ra4/t0cki ra5/an4/ss v ss osc1/clkin osc2/ clkout rc0/t1oso/t1cki rc1/t1osi rc2/ccp1 rc3/sck/scl rb7/pgd rb6/pgc rb5 rb4 rb3/pgm rb2 rb1 rb0/int v dd v ss rc7 rc6 rc5/sdo rc4/sdi/sda dip, soic, ssop pic16f872 28-pin, 8-bit cmos flash microcontroller
pic16f872 ds30221a-page 2 preliminary 1999 microchip technology inc. key features picmicro? mid-range reference manual (ds33023) pic16f872 operating frequency dc - 20 mhz resets (and delays) por, bor (pwrt, ost) flash program memory (14-bit words) 2k data memory (bytes) 128 eeprom data memory 64 interrupts 10 i/o ports ports a,b,c timers 3 capture/compare/pwm module 1 serial communications mssp 10-bit analog-to-digital module 5 input channels instruction set 35 instructions
? 1999 microchip technology inc. preliminary ds30221a-page 3 pic16f872 table of contents 1.0 device overview ............................................................................................................. .............................................................. 5 2.0 memory organization......................................................................................................... ........................................................... 7 3.0 i/o ports................................................................................................................... ................................................................... 23 4.0 data eeprom and flash program memory ....................................................................................... ................................... 29 5.0 timer0 module ............................................................................................................... ............................................................. 37 6.0 timer1 module ............................................................................................................... ............................................................. 41 7.0 timer2 module ............................................................................................................... ............................................................ 45 8.0 capture/compare/pwm (ccp) module(s)......................................................................................... ......................................... 47 9.0 master synchronous serial port (mssp) module................................................................................ ....................................... 53 10.0 analog-to-digital converter (a/d) module ................................................................................... ............................................... 85 11.0 special features of the cpu ................................................................................................ ...................................................... 95 12.0 instruction set summary.................................................................................................... ....................................................... 111 13.0 development support ........................................................................................................ ....................................................... 119 14.0 electrical characteristics................................................................................................. .......................................................... 125 15.0 dc and ac characteristics graphs and tables ................................................................................ ....................................... 143 16.0 packaging information ...................................................................................................... ........................................................ 145 appendix a: revision history.................................................................................................... ..................................................... 149 appendix b: conversion considerations........................................................................................... ............................................. 149 index .......................................................................................................................... ......................................................... 151 on-line support................................................................................................................ ................................................................. 157 product identification system .................................................................................................. .......................................................... 159 to our valued customers most current data sheet to obtain the most up-to-date version of this data sheet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the version number. e.g., ds30000a is version a of document ds30000. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. errata an errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the re vi- sion of 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pic16f872 ds30221a-page 4 preliminary ? 1999 microchip technology inc. notes:
? 1999 microchip technology inc. preliminary ds30221a-page 5 pic16f872 1.0 device overview this document contains device-specific information. additional information may be found in the picmicro? mid-range reference manual, (ds33023), which may be obtained from your local microchip sales represen- tative or downloaded from the microchip website. the reference manual should be considered a comple- mentary document to this data sheet, and is highly rec- ommended reading for a better understanding of the device architecture and operation of the peripheral modules. this data sheet covers the pic16f872 device. the pic16f872 is a 28-pin device and its block diagram is shown in figure 1-1. figure 1-1: pic16f872 block diagram flash program memory 13 data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) ram file registers direct addr 7 ram addr (1) 9 addr mux indirect addr fsr reg status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/clkin osc2/clkout mclr v dd , v ss porta portb portc ra4/t0cki ra5/an4/ss rb0/int rc0/t1oso/t1cki rc1/t1osi rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6 rc7 8 8 brown-out reset note 1: higher order bits are from the status register. ccp1 synchronous 10-bit a/d timer0 timer1 timer2 serial port ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0 8 3 data eeprom rb1 rb2 rb3/pgm rb4 rb5 rb6/pgc rb7/pgd device program flash data memory data eeprom pic16f872 2k 128 bytes 64 bytes in-circuit debugger low-voltage programming
pic16f872 ds30221a-page 6 preliminary ? 1999 microchip technology inc. table 1-1: pic16f872 pinout description pin name dip pin# soic pin# i/o/p type buffer type description osc1/clkin 9 9 i st/cmos (3) oscillator crystal input/external clock source input. osc2/clkout 10 10 o oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, the osc2 pin outputs clkout, which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. mclr /v pp /thv 1 1 i/p st master clear (reset) input or programming voltage input or high voltage test mode control. this pin is an active low reset to the device. porta is a bi-directional i/o port. ra0/an0 2 2 i/o ttl ra0 can also be analog input0. ra1/an1 3 3 i/o ttl ra1 can also be analog input1. ra2/an2/v ref - 4 4 i/o ttl ra2 can also be analog input2 or negative analog reference voltage. ra3/an3/v ref + 5 5 i/o ttl ra3 can also be analog input3 or positive analog reference voltage. ra4/t0cki 6 6 i/o st ra4 can also be the clock input to the timer0 module. output is open drain type. ra5/ss/ an4 7 7 i/o ttl ra5 can also be analog input4 or the slave select for the synchronous serial port. portb is a bi-directional i/o port. portb can be software programmed for internal weak pull-up on all inputs. rb0/int 21 21 i/o ttl/st (1) rb0 can also be the external interrupt pin. rb1 22 22 i/o ttl rb2 23 23 i/o ttl rb3/pgm 24 24 i/o ttl/st (1) rb3 can also be the low voltage programming input. rb4 25 25 i/o ttl interrupt on change pin. rb5 26 26 i/o ttl interrupt on change pin. rb6/pgc 27 27 i/o ttl/st (2) interrupt on change pin or in-circuit debugger pin. serial programming clock. rb7/pgd 28 28 i/o ttl/st (2) interrupt on change pin or in-circuit debugger pin. serial programming data. portc is a bi-directional i/o port. rc0/t1oso/t1cki 11 11 i/o st rc0 can also be the timer1 oscillator output or timer1 clock input. rc1/t1osi 12 12 i/o st rc1 can also be the timer1 oscillator input. rc2/ccp1 13 13 i/o st rc2 can also be the capture1 input/compare1 output/pwm1 output. rc3/sck/scl 14 14 i/o st rc3 can also be the synchronous serial clock input/output for both spi and i 2 c modes. rc4/sdi/sda 15 15 i/o st rc4 can also be the spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo 16 16 i/o st rc5 can also be the spi data out (spi mode). rc6 17 17 i/o st rc7 18 18 i/o st v ss 8, 19 8, 19 p ground reference for logic and i/o pins. v dd 20 20 p positive supply for logic and i/o pins. legend: i = input o = output i/o = input/output p = power = not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured as the external interrupt or lvp. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when configured in rc oscillator mode and a cmos input otherwise.
? 1999 microchip technology inc. preliminary ds30221a-page 7 pic16f872 2.0 memory organization there are three memory blocks in each of these picmicro ? mcus. the program memory and data memory have separate buses, so that concurrent access can occur, and is detailed in this section. the eeprom data memory block is detailed in section 4.0. additional information on device memory may be found in the picmicro ? mid-range reference manual, (ds33023). 2.1 program memory organization the pic16f872 devices have a 13-bit program counter capable of addressing an 8k x 14 program memory space. the pic16f872 device has 2k x 14 words of flash program memory. accessing a location above the physically implemented address will cause a wrap- around. the reset vector is at 0000h and the interrupt vector is at 0004h. figure 2-1: pic16f872 program memory map and stack 2.2 data memory organization the data memory is partitioned into multiple banks which contain the general purpose registers and the special function registers. bits rp1(status<6>) and rp0 (status<5>) are the bank select bits. each bank extends up to 7fh (128 bytes). the lower locations of each bank are reserved for the special function registers. above the special function regis- ters are general purpose registers, implemented as static ram. all implemented banks contain special function re gisters. some high use special function registers from one bank may be mirrored in another bank for code reduction and quicker access. 2.2.1 general purpose register file the register file can be accessed either directly, or indi- rectly through the file select register fsr. pc<12:0> 13 0000h 0004h 0005h stack level 1 stack level 8 reset vector interrupt vector on-chip call, return retfie, retlw 1fffh stack level 2 program memory page 0 07ffh 0800h rp<1:0> bank 00 0 01 1 10 2 11 3 note: eeprom data memory description can be found in section 4.0 of this data sheet
pic16f872 ds30221a-page 8 preliminary ? 1999 microchip technology inc. figure 2-2: pic16f872 register file map indirect addr. (*) tmr0 pcl status fsr porta portb portc pclath intcon pir1 tmr1l tmr1h t1con tmr2 t2con sspbuf sspcon ccpr1l ccpr1h ccp1con option_reg pcl status fsr trisa trisb trisc pclath intcon pie1 pcon pr2 sspadd sspstat 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh 20h a0h 7fh ffh bank 0 bank 1 file address indirect addr. (*) indirect addr. (*) pcl status fsr pclath intcon pcl status fsr pclath intcon 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10ah 10bh 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18ah 18bh 17fh 1ffh bank 2 bank 3 indirect addr. (*) adresl tmr0 option_reg pir2 pie2 adresh adcon0 adcon1 general purpose register general purpose register 1efh 1f0h accesses a0h - bfh 16fh 170h accesses 70h-7fh trisb portb 96 bytes 32 bytes sspcon2 10ch 10dh 10eh 10fh 110h 18ch 18dh 18eh 18fh 190h eedata eeadr eecon1 eecon2 eedath eeadrh reserved (1) reserved (1) unimplemented data memory locations, read as '0'. * not a physical register. note 1: these registers are reserved; maintain these registers clear. 120h 1a0h accesses 70h-7fh accesses 70h-7fh accesses 20h-7fh c0h efh f0h 1c0h 1bfh bfh
? 1999 microchip technology inc. preliminary ds30221a-page 9 pic16f872 2.2.2 special function registers the special function registers are registers used by the cpu and peripheral modules for controlling the desired operation of the device. these registers are implemented as static ram. a list of these registers is given in table 2-1. the special function registers can be classified into two sets: core (cpu) and peripheral. those registers associated with the core functions are described in detail in this section. those related to the operation of the peripheral features are described in detail in the peripheral feature section. table 2-1: special function register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (2) bank 0 00h (3) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 01h tmr0 timer0 modules register xxxx xxxx uuuu uuuu 02h (3) pcl program counter's (pc) least significant byte 0000 0000 0000 0000 03h (3) status irp rp1 rp0 to pd zdcc 0001 1xxx 000q quuu 04h (3) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 05h porta porta data latch when written: porta pins when read --0x 0000 --0u 0000 06h portb portb data latch when written: portb pins when read xxxx xxxx uuuu uuuu 07h portc portc data latch when written: portc pins when read xxxx xxxx uuuu uuuu 08h unimplemented 09h unimplemented 0ah (1,3) pclath write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 0bh (3) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 (4) adif (4) (4) sspif ccp1if tmr2if tmr1if r0rr 0000 r0rr 0000 0dh pir2 (4) eeif bclif (4) -r-0 0--r -r-0 0--r 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu 11h tmr2 timer2 modules register 0000 0000 0000 0000 12h t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 15h ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 18h unimplemented 19h unimplemented 1ah unimplemented 1bh unimplemented 1ch unimplemented 1dh unimplemented 1eh adresh a/d result register high byte xxxx xxxx uuuu uuuu 1fh adcon0 adcs1 adcs0 chs2 chs1 chs0 go/ done adon 0000 00-0 0000 00-0 legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', r = reserved. shaded locations are unimplemented, read as 0. note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8> whose contents are transferred to the upper byte of the program counter. 2: other (non power-up) resets include external reset through mclr and watchdog timer reset. 3: these registers can be addressed from any bank. 4: these bits are reserved; always maintain these bits clear.
pic16f872 ds30221a-page 10 preliminary ? 1999 microchip technology inc. bank 1 80h (3) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 81h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 82h (3) pcl program counter's (pc) least significant byte 0000 0000 0000 0000 83h (3) status irp rp1 rp0 to pd zdcc 0001 1xxx 000q quuu 84h (3) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 85h trisa porta data direction register --11 1111 --11 1111 86h trisb portb data direction register 1111 1111 1111 1111 87h trisc portc data direction register 1111 1111 1111 1111 88h unimplemented 89h unimplemented 8ah (1,3) pclath write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 8bh (3) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 8ch pie1 (4) adie (4) (4) sspie ccp1ie tmr2ie tmr1ie r0rr 0000 r0rr 0000 8dh pie2 (4) eeie bclie (4) -r-0 0--r -r-0 0--r 8eh pcon por bor ---- --qq ---- --uu 8fh unimplemented 90h unimplemented 91h sspcon2 gcen ackstat ackdt acken rcen pen rsen sen 0000 0000 0000 0000 92h pr2 timer2 period register 1111 1111 1111 1111 93h sspadd synchronous serial port (i 2 c mode) address register 0000 0000 0000 0000 94h sspstat smp cke d/a psr/w ua bf 0000 0000 0000 0000 95h unimplemented 96h unimplemented 97h unimplemented 98h unimplemented 99h unimplemented 9ah unimplemented 9bh unimplemented 9ch unimplemented 9dh unimplemented 9eh adresl a/d result register low byte xxxx xxxx uuuu uuuu 9fh adcon1 adfm pcfg3 pcfg2 pcfg1 pcfg0 0--- 0000 0--- 0000 table 2-1: special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (2) legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', r = reserved. shaded locations are unimplemented, read as 0. note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8> whose contents are transferred to the upper byte of the program counter. 2: other (non power-up) resets include external reset through mclr and watchdog timer reset. 3: these registers can be addressed from any bank. 4: these bits are reserved; always maintain these bits clear.
? 1999 microchip technology inc. preliminary ds30221a-page 11 pic16f872 bank 2 100h (3) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 101h tmr0 timer0 modules register xxxx xxxx uuuu uuuu 102h (3) pcl program counter's (pc) least significant byte 0000 0000 0000 0000 103h (3) status irp rp1 rp0 to pd z dc c 0001 1xxx 000q quuu 104h (3) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 105h unimplemented 106h portb portb data latch when written: portb pins when read xxxx xxxx uuuu uuuu 107h unimplemented 108h unimplemented 109h unimplemented 10ah (1,3) pclath write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 10bh (3) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 10ch eedata eeprom data register xxxx xxxx uuuu uuuu 10dh eeadr eeprom address register xxxx xxxx uuuu uuuu 10eh eedath eeprom data register high byte xxxx xxxx uuuu uuuu 10fh eeadrh eeprom address register high byte xxxx xxxx uuuu uuuu bank 3 180h (3) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 181h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 182h (3) pcl program counter's (pc) least significant byte 0000 0000 0000 0000 183h (3) status irp rp1 rp0 to pd z dc c 0001 1xxx 000q quuu 184h (3) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 185h unimplemented 186h trisb portb data direction register 1111 1111 1111 1111 187h unimplemented 188h unimplemented 189h unimplemented 18ah (1,3) pclath write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 18bh (3) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 18ch eecon1 eepgd wrerr wren wr rd x--- x000 x--- u000 18dh eecon2 eeprom control register2 (not a physical register) ---- ---- ---- ---- 18eh reserved maintain clear 0000 0000 0000 0000 18fh reserved maintain clear 0000 0000 0000 0000 table 2-1: special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (2) legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', r = reserved. shaded locations are unimplemented, read as 0. note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8> whose contents are transferred to the upper byte of the program counter. 2: other (non power-up) resets include external reset through mclr and watchdog timer reset. 3: these registers can be addressed from any bank. 4: these bits are reserved; always maintain these bits clear.
pic16f872 ds30221a-page 12 preliminary ? 1999 microchip technology inc. 2.2.2.1 status register the status register contains the arithmetic status of the alu, the reset status and the bank select bits for data memory. the status register can be the destination for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable, therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper-three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). it is recommended, therefore, that only bcf, bsf, swapf and movwf instructions are used to alter the status register, because these instructions do not affect the z, c or dc bits from the status register. for other instructions not affecting any status bits, see the "instruction set summary." register 2-1: status register (address 03h, 83h, 103h, 183h) note: the c and dc bits operate as a borrow and digit borrow bit, respectively, in sub- traction. see the sublw and subwf instructions for examples. r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x irp rp1 rp0 to pd z dc c r = readable bit w = writable bit u = unimplemented bit, read as 0 - n= value at por reset bit7 bit0 bit 7: irp: register bank select bit (used for indirect addressing) 1 = bank 2, 3 (100h - 1ffh) 0 = bank 0, 1 (00h - ffh) bit 6-5: rp<1:0> : register bank select bits (used for direct addressing) 11 = bank 3 (180h - 1ffh) 10 = bank 2 (100h - 17fh) 01 = bank 1 (80h - ffh) 00 = bank 0 (00h - 7fh) each bank is 128 bytes bit 4: to : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3: pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2: z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1: dc : digit carry/borrow bit ( addwf , addlw,sublw,subwf instructions) (for borrow the polarity is reversed) 1 = a carry-out from the 4th low order bit of the result occurred 0 = no carry-out from the 4th low order bit of the result bit 0: c : carry/borrow bit ( addwf , addlw,sublw,subwf instructions) 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note: for borrow the polarity is reversed. a subtraction is executed by adding the twos complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either the high or low order bit of the source register.
? 1999 microchip technology inc. preliminary ds30221a-page 13 pic16f872 2.2.2.2 option_reg register the option_reg register is a readable and writable register, which contains various control bits to configure the tmr0 prescaler/wdt postscaler (single assign- able register known also as the prescaler), the external int interrupt, tmr0 and the weak pull-ups on portb. register 2-2: option_reg register (address 81h, 181h) note: to achieve a 1:1 prescaler assignment for the tmr0 register, assign the prescaler to the watchdog timer. r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg t0cs t0se psa ps2 ps1 ps0 r = readable bit w = writable bit u = unimplemented bit, read as 0 - n= value at por reset bit7 bit0 bit 7: rbpu : portb pull-up enable bit 1 = portb pull-ups are disabled 0 = portb pull-ups are enabled by individual port latch values bit 6: intedg : interrupt edge select bit 1 = interrupt on rising edge of rb0/int pin 0 = interrupt on falling edge of rb0/int pin bit 5: t0cs : tmr0 clock source select bit 1 = transition on ra4/t0cki pin 0 = internal instruction cycle clock (clkout) bit 4: t0se : tmr0 source edge select bit 1 = increment on high-to-low transition on ra4/t0cki pin 0 = increment on low-to-high transition on ra4/t0cki pin bit 3: psa : prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0: ps<2:0> : prescaler rate select bits note: when using low voltage icsp programming (lvp) and the pull-ups on portb are enabled, bit 3 in the trisb register must be cleared to disable the pull-up on rb3 and ensure the proper operation of the device. 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate
pic16f872 ds30221a-page 14 preliminary ? 1999 microchip technology inc. 2.2.2.3 intcon register the intcon register is a readable and writable regis- ter, which contains various enable and flag bits for the tmr0 register overflow, rb port change and external rb0/int pin interrupts. register 2-3: intcon register (address 0bh, 8bh, 10bh, 18bh) note: interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie peie t0ie inte rbie t0if intf rbif r = readable bit w = writable bit u = unimplemented bit, read as 0 - n= value at por reset bit7 bit0 bit 7: gie: global interrupt enable bit 1 = enables all un-masked interrupts 0 = disables all interrupts bit 6: peie : peripheral interrupt enable bit 1 = enables all un-masked peripheral interrupts 0 = disables all peripheral interrupts bit 5: t0ie : tmr0 overflow interrupt enable bit 1 = enables the tmr0 interrupt 0 = disables the tmr0 interrupt bit 4: inte : rb0/int external interrupt enable bit 1 = enables the rb0/int external interrupt 0 = disables the rb0/int external interrupt bit 3: rbie : rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2: t0if : tmr0 overflow interrupt flag bit 1 = tmr0 register has overflowed (must be cleared in software) 0 = tmr0 register did not overflow bit 1: intf : rb0/int external interrupt flag bit 1 = the rb0/int external interrupt occurred (must be cleared in software) 0 = the rb0/int external interrupt did not occur bit 0: rbif : rb port change interrupt flag bit 1 = at least one of the rb<7:4> pins changed state (must be cleared in software) 0 = none of the rb<7:4> pins have changed state
? 1999 microchip technology inc. preliminary ds30221a-page 15 pic16f872 2.2.2.4 pie1 register the pie1 register contains the individual enable bits for the peripheral interrupts. register 2-4: pie1 register (address 8ch) note: bit peie (intcon<6>) must be set to enable any peripheral interrupt. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adie sspie ccp1ie tmr2ie tmr1ie r = readable bit w = writable bit u = unimplemented bit, read as 0 - n= value at por reset bit7 bit0 bit 7: reserved: always maintain this bit clear bit 6: adie : a/d converter interrupt enable bit 1 = enables the a/d converter interrupt 0 = disables the a/d converter interrupt bit 5-4: reserved: always maintain this bit clear bit 3: sspie : synchronous serial port interrupt enable bit 1 = enables the ssp interrupt 0 = disables the ssp interrupt bit 2: ccp1ie : ccp1 interrupt enable bit 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit 1: tmr2ie : tmr2 to pr2 match interrupt enable bit 1 = enables the tmr2 to pr2 match interrupt 0 = disables the tmr2 to pr2 match interrupt bit 0: tmr1ie : tmr1 overflow interrupt enable bit 1 = enables the tmr1 overflow interrupt 0 = disables the tmr1 overflow interrupt
pic16f872 ds30221a-page 16 preliminary ? 1999 microchip technology inc. 2.2.2.5 pir1 register the pir1 register contains the individual flag bits for the peripheral interrupts. register 2-5: pir1 register (address 0ch) note: interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt bits are clear prior to enabling an interrupt. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adif sspif ccp1if tmr2if tmr1if r = readable bit w = writable bit u = unimplemented bit, read as 0 - n= value at por reset bit7 bit0 bit 7: reserved: always maintain this bit clear bit 6: adif : a/d converter interrupt flag bit 1 = an a/d conversion completed 0 = the a/d conversion is not complete bit 5-4: reserved: always maintain this bit clear bit 3: sspif : synchronous serial port (ssp) interrupt flag 1 = the ssp interrupt condition has occurred, and must be cleared in software before returning from the interrupt service routine. the conditions that will set this bit are: spi a transmission/reception has taken place. i 2 c slave a transmission/reception has taken place. i 2 c master a transmission/reception has taken place. the initiated start condition was completed by the ssp module. the initiated stop condition was completed by the ssp module. the initiated restart condition was completed by the ssp module. the initiated acknowledge condition was completed by the ssp module. a start condition occurred while the ssp module was idle (multimaster system). a stop condition occurred while the ssp module was idle (multimaster system). 0 = no ssp interrupt condition has occurred. bit 2: ccp1if : ccp1 interrupt flag bit capture mode 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode unused in this mode bit 1: tmr2if : tmr2 to pr2 match interrupt flag bit 1 = tmr2 to pr2 match occurred (must be cleared in software) 0 = no tmr2 to pr2 match occurred bit 0: tmr1if : tmr1 overflow interrupt flag bit 1 = tmr1 register overflowed (must be cleared in software) 0 = tmr1 register did not overflow
? 1999 microchip technology inc. preliminary ds30221a-page 17 pic16f872 2.2.2.6 pie2 register the pie2 register contains the individual enable bits for the ssp bus collision interrupt and the eeprom write operation interrupt. register 2-6: pie2 register (address 8dh) u-0 r/w-0 u-0 r/w-0 r/w-0 u-0 u-0 r/w-0 eeie bclie r = readable bit w = writable bit u = unimplemented bit, read as 0 - n= value at por reset bit7 bit0 bit 7: unimplemented: read as '0' bit 6: reserved : always maintain this bit clear bit 5: unimplemented: read as '0' bit 4: eeie : eeprom write operation interrupt enable 1 = enable ee write interrupt 0 = disable ee write interrupt bit 3: bclie : bus collision interrupt enable 1 = enable bus collision interrupt 0 = disable bus collision interrupt bit 2-1: unimplemented: read as '0' bit 0: reserved : always maintain this bit clear
pic16f872 ds30221a-page 18 preliminary ? 1999 microchip technology inc. 2.2.2.7 pir2 register the pir2 register contains the flag bits for the ssp bus collision interrupt and the eeprom write operation interrupt. . register 2-7: pir2 register (address 0dh) note: interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. u-0 r/w-0 u-0 r/w-0 r/w-0 u-0 u-0 r/w-0 eeif bclif r = readable bit w = writable bit u = unimplemented bit, read as 0 - n= value at por reset bit7 bit0 bit 7: unimplemented: read as '0' bit 6: reserved: always maintain this bit clear bit 5: unimplemented: read as '0' bit 4: eeif : eeprom write operation interrupt flag bit 1 = the write operation completed (must be cleared in software) 0 = the write operation is not complete or has not been started bit 3: bclif : bus collision interrupt flag 1 = a bus collision has occurred in the ssp, when configured for i 2 c master mode 0 = no bus collision has occurred bit 2-1: unimplemented: read as '0' bit 0: reserved: always maintain this bit clear
? 1999 microchip technology inc. preliminary ds30221a-page 19 pic16f872 2.2.2.8 pcon register the power control (pcon) register contains flag bits to allow differentiation between a power-on reset (por), a brown-out reset (bor), a watch-dog reset (wdt) and an external mclr reset. register 2-8: pcon register (address 8eh) note: bor is unknown on por. it must be set by the user and checked on subsequent resets to see if bor is clear, indicating a brown-out has occurred. the bor status bit is a dont care and is not predictable if the brown-out circuit is disabled (by clear- ing the boden bit in the configuration word). u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-1 por bor r = readable bit w = writable bit u = unimplemented bit, read as 0 - n= value at por reset bit7 bit0 bit 7-2: unimplemented: read as '0' bit 1: por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0: bor : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs)
pic16f872 ds30221a-page 20 preliminary ? 1999 microchip technology inc. 2.3 pcl and pclath the program counter (pc) is 13-bits wide. the low byte comes from the pcl register, which is a readable and writable register. the upper bits (pc<12:8>) are not readable, but are indirectly writable through the pclath register. on any reset, the upper bits of the pc will be cleared. figure 2-3 shows the two situations for the loading of the pc. the upper example in the fig- ure shows how the pc is loaded on a write to pcl (pclath<4:0> ? pch). the lower example in the fig- ure shows how the pc is loaded during a call or goto instruction (pclath<4:3> ? pch). figure 2-3: loading of pc in different situations 2.3.1 computed goto a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). when doing a table read using a computed goto method, care should be exercised if the table location crosses a pcl memory boundary (each 256 byte block). refer to the application note, implementing a table read" (an556). 2.3.2 stack the pic16cxx family has an 8-level deep x 13-bit wide hardware stack. the stack space is not part of either program or data space and the stack pointer is not readable or writable. the pc is pushed onto the stack when a call instruction is executed or an interrupt causes a branch. the stack is poped in the event of a return,retlw or a retfie instruction execution. pclath is not affected by a push or pop operation. the stack operates as a circular buffer. this means that after the stack has been pushed eight times, the ninth push overwrites the value that was stored from the first push. the tenth push overwrites the second push (and so on). 2.4 program memory paging the pic16cxxx architecture is capable of addressing a continuous 8k word block of program memory. the call and goto instructions provide 11 bits of the address, which allows branches within any 2k program memory page. therefore, the 8k words of program memory are broken into four pages. since the pic16fc872 has only 2k words of program memory or one page, additional code is not required to ensure that the correct page is selected before a call or goto instruction is executed. the pclath<4:3> bits should always be maintained as zeros. if a return from a call instruction (or interrupt) is executed, the entire 13-bit pc is popped off the stack. manipulation of the pclath is not required for the return instructions. 2.5 indirect addressing, indf and fsr registers the indf register is not a physical register. addressing the indf register will cause indirect addressing. indirect addressing is possible by using the indf reg- ister. any instruction using the indf register actually accesses the register pointed to by the file select reg- ister, fsr. reading the indf register itself indirectly (fsr = '0') will read 00h. writing to the indf register indirectly results in a no-operation (although status bits may be affected). an effective 9-bit address is obtained by concatenating the 8-bit fsr register and the irp bit (status<7>), as shown in figure 2-4. a simple program to clear ram locations 20h-2fh using indirect addressing is shown in example 2-1. example 2-1: indirect addressing movlw 0x20 ;initialize pointer movwf fsr ;to ram next clrf indf ;clear indf register incf fsr,f ;inc pointer btfss fsr,4 ;all done? goto next ;no clear next continue : ;yes continue pc 12 8 7 0 5 pclath<4:0> pclath instruction with alu goto,call opcode <10:0> 8 pc 12 11 10 0 11 pclath<4:3> pch pcl 87 2 pclath pch pcl pcl as destination note 1: there are no status bits to indicate stack overflow or stack underflow conditions. 2: there are no instructions/mnemonics called push or pop . these are actions that occur from the execution of the call, return, retlw and retfie instruc- tions or the vectoring to an interrupt address.
? 1999 microchip technology inc. preliminary ds30221a-page 21 pic16f872 figure 2-4: direct/indirect addressing note 1: for register file map detail see figure 2-2. data memory (1) indirect addressing direct addressing bank select location select rp1:rp0 6 0 from opcode irp fsr register 7 0 bank select location select 00 01 10 11 bank 0 bank 1 bank 2 bank 3 ffh 80h 7fh 00h 17fh 100h 1ffh 180h
pic16f872 ds30221a-page 22 preliminary ? 1999 microchip technology inc. notes:
? 1999 microchip technology inc. preliminary ds30221a-page 23 pic16f872 3.0 i/o ports some pins for these i/o ports are multiplexed with an alternate function for the peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. additional information on i/o ports may be found in the picmicro? mid-range reference manual, (ds33023). 3.1 porta and the trisa register porta is a 6-bit wide, bi-directional port. the corre- sponding data direction register is trisa. setting a trisa bit (=1) will make the corresponding porta pin an input (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trisa bit (=0) will make the corresponding porta pin an output (i.e., put the contents of the output latch on the selected pin). reading the porta register reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, the value is modified and then written to the port data latch. pin ra4 is multiplexed with the timer0 module clock input to become the ra4/t0cki pin. the ra4/t0cki pin is a schmitt trigger input and an open drain output. all other porta pins have ttl input levels and full cmos output drivers. other porta pins are multiplexed with analog inputs and analog v ref input. the operation of each pin is selected by clearing/setting the control bits in the adcon1 register (a/d control register1). the trisa register controls the direction of the ra pins, even when they are being used as analog inputs. the user must ensure the bits in the trisa register are maintained set when using them as analog inputs. example 3-1: initializing porta bcf status, rp0 ; bcf status, rp1 ; bank0 clrf porta ; initialize porta by ; clearing output ; data latches bsf status, rp0 ; select bank 1 movlw 0x06 ; configure all pins movwf adcon1 ; as digital inputs movlw 0xcf ; value used to ; initialize data ; direction movwf trisa ; set ra<3:0> as inputs ; ra<5:4> as outputs ; trisa<7:6> are always ; read as '0'. figure 3-1: block diagram of ra<3:0> and ra5 pins figure 3-2: block diagram of ra4/ t0cki pin note: on a power-on reset, these pins are con- figured as analog inputs and read as '0'. data bus q d q ck q d q ck qd en p n wr port wr tris data latch tris latch rd tris rd port v ss v dd i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . analog input mode ttl input buffer to a/d converter data bus wr port wr tris rd port data latch tris latch rd tris schmitt trigger input buffer n v ss i/o pin (1) tmr0 clock input q d q ck q d q ck en qd en note 1: i/o pin has protection diodes to v ss only.
pic16f872 ds30221a-page 24 preliminary ? 1999 microchip technology inc. table 3-1: porta functions table 3-2: summary of registers associated with porta name bit# buffer function ra0/an0 bit0 ttl input/output or analog input ra1/an1 bit1 ttl input/output or analog input ra2/an2 bit2 ttl input/output or analog input ra3/an3/v ref bit3 ttl input/output or analog input or v ref ra4/t0cki bit4 st input/output or external clock input for timer0 output is open drain type ra5/ss /an4 bit5 ttl input/output or slave select input for synchronous serial port or analog input legend: ttl = ttl input, st = schmitt trigger input. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 05h porta ra5 ra4 ra3 ra2 ra1 ra0 --0x 0000 --0u 0000 85h trisa porta data direction register --11 1111 --11 1111 9fh adcon1 adfm pcfg3 pcfg2 pcfg1 pcfg0 --0- 0000 --0- 0000 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by porta. note: when using the ssp module in spi slave mode and ss enabled, the a/d converter must be set to one of the following modes where pcfg<3:0> = 0100,0101, 011x, 1101, 1110, 1111 .
? 1999 microchip technology inc. preliminary ds30221a-page 25 pic16f872 3.2 portb and the trisb register portb is an 8-bit wide bi-directional port. the corre- sponding data direction register is trisb. setting a trisb bit (=1) will make the corresponding portb pin an input (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trisb bit (=0) will make the corresponding portb pin an output (i.e., put the contents of the output latch on the selected pin). three pins of portb are multiplexed with the low voltage programming function; rb3/pgm, rb6/pgc and rb7/pgd. the alternate functions of these pins are described in the special features section. each of the portb pins has a weak internal pull-up. a single control bit can turn on all the pull-ups. this is per- formed by clearing bit rbpu (option_reg<7>). the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are dis- abled on a power-on reset. figure 3-3: block diagram of rb<3:0> pins four of portbs pins, rb<7:4>, have an interrupt on change feature. only pins configured as inputs can cause this interrupt to occur (i.e., any rb<7:4> pin con- figured as an output is excluded from the interrupt on change comparison). the input pins (of rb<7:4>) are compared with the old value latched on the last read of portb. the mismatch outputs of rb<7:4> are ored together to generate the rb port change inter- rupt with flag bit rbif (intcon<0>). this interrupt can wake the device from sleep. the user, in the interrupt service routine, can clear the inter- rupt in the following manner: a) any read or write of portb. this will end the mismatch condition. b) clear flag bit rbif. a mismatch condition will continue to set flag bit rbif. reading portb will end the mismatch condition and allow flag bit rbif to be cleared. the interrupt on change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt on change feature. polling of portb is not recommended while using the interrupt on change feature. this interrupt on mismatch feature, together with soft- ware configurable pull-ups on these four pins, allow easy interface to a keypad and make it possible for wake-up on key-depression. refer to the embedded control handbook, implementing wake-up on key stroke (an552). rb0/int is an external interrupt input pin and is config- ured using the intedg bit (option_reg<6>). rb0/int is discussed in detail in section 11.10.1. figure 3-4: block diagram of rb<7:4> pins data latch rbpu (2) p v dd q d ck q d ck qd en data bus wr port wr tris rd tris rd port weak pull-up rd port rb0/int i/o pin (1) ttl input buffer schmitt trigger buffer tris latch note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (option_reg<7>). rb3/pgm data latch from other rbpu (2) p v dd i/o q d ck q d ck qd en qd en data bus wr port wr tris set rbif tris latch rd tris rd port rb<7:4> pins weak pull-up rd port latch ttl input buffer pin (1) st buffer rb<7:6> in serial programming mode q3 q1 note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (option_reg<7>). note: when using low voltage icsp programming (lvp) and the pull-ups on portb are enabled, bit 3 in the trisb register must be cleared to disable the pull-up on rb3 and ensure the proper operation of the device.
pic16f872 ds30221a-page 26 preliminary ? 1999 microchip technology inc. table 3-3: portb functions table 3-4: summary of registers associated with portb name bit# buffer function rb0/int bit0 ttl/st (1) input/output pin or external interrupt input. internal software programmable weak pull-up. rb1 bit1 ttl input/output pin. internal software programmable weak pull-up. rb2 bit2 ttl input/output pin. internal software programmable weak pull-up. rb3/pgm bit3 ttl/st (1) input/output pin or programming pin in lvp mode. internal software programmable weak pull-up. rb4 bit4 ttl input/output pin (with interrupt on change). internal software programmable weak pull-up. rb5 bit5 ttl input/output pin (with interrupt on change). internal software programmable weak pull-up. rb6/pgc bit6 ttl/st (2) input/output pin (with interrupt on change) or in-circuit debugger pin. internal software programmable weak pull-up. serial programming clock. rb7/pgd bit7 ttl/st (2) input/output pin (with interrupt on change) or in-circuit debugger pin. internal software programmable weak pull-up. serial programming data. legend: ttl = ttl input, st = schmitt trigger input. note 1: this buffer is a schmitt trigger input when configured as the external interrupt or lvp mode. 2: this buffer is a schmitt trigger input when used in serial programming mode. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 06h, 106h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu 86h, 186h trisb portb data direction register 1111 1111 1111 1111 81h, 181h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: x = unknown, u = unchanged. shaded cells are not used by portb.
? 1999 microchip technology inc. preliminary ds30221a-page 27 pic16f872 3.3 portc and the trisc register portc is an 8-bit wide, bi-directional port. the corre- sponding data direction register is trisc. setting a trisc bit (=1) will make the corresponding portc pin an input (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trisc bit (=0) will make the corresponding portc pin an output (i.e., put the contents of the output latch on the selected pin). portc is multiplexed with several peripheral functions (table 3-5). portc pins have schmitt trigger input buffers. when the i 2 c module is enabled, the portc (3:4) pins can be configured with normal i 2 c levels or with smbus levels by using the cke bit (sspstat<6>). when enabling peripheral functions, care should be taken in defining tris bits for each portc pin. some peripherals override the tris bit to make a pin an out- put, while other peripherals override the tris bit to make a pin an input. since the tris bit override is in effect while the peripheral is enabled, read-modify- write instructions ( bsf, bcf, xorwf ) with trisc as destination should be avoided. the user should refer to the corresponding peripheral section for the correct tris bit settings. figure 3-5: portc block diagram (peripheral output override) rc<0:2> rc<5:7> figure 3-6: portc block diagram (peripheral output override) rc<3:4> port/peripheral select (2) data bus wr port wr tris rd data latch tris latch rd tris schmitt tr i g g e r q d q ck qd en peripheral data out 0 1 q d q ck p n v dd v ss port peripheral oe (3) peripheral input i/o pin (1) note 1: i/o pins have diode protection to v dd and v ss . 2: port/peripheral select signal selects between port data and peripheral output. 3: peripheral oe (output enable) is only activated if peripheral select is active. port/peripheral select (2) data bus wr port wr tris rd data latch tris latch rd tris schmitt trigger q d q ck qd en peripheral data out 0 1 q d q ck p n v dd vss port peripheral oe (3) sspl input i/o pin (1) note 1: i/o pins have diode protection to v dd and v ss . 2: port/peripheral select signal selects between port data and peripheral output. 3: peripheral oe (output enable) is only activated if peripheral select is active. 0 1 cke sspstat<6> schmitt tr i g g e r with smbus levels
pic16f872 ds30221a-page 28 preliminary ? 1999 microchip technology inc. table 3-5: portc functions table 3-6: summary of registers associated with portc name bit# buffer type function rc0/t1oso/t1cki bit0 st input/output port pin or timer1 oscillator output/timer1 clock input. rc1/t1osi bit1 st input/output port pin or timer1 oscillator input. rc2/ccp1 bit2 st input/output port pin or capture1 input/compare1 output/pwm1 output. rc3/sck/scl bit3 st rc3 can also be the synchronous serial clock for both spi and i 2 c modes. rc4/sdi/sda bit4 st rc4 can also be the spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo bit5 st input/output port pin or synchronous serial port data output. rc6 bit6 st input/output port pin. rc7 bit7 st input/output port pin. legend: st = schmitt trigger input. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 07h portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu 87h trisc portc data direction register 1111 1111 1111 1111 legend: x = unknown, u = unchanged.
? 1999 microchip technology inc. preliminary ds30221a-page 29 pic16f872 4.0 data eeprom and flash program memory the data eeprom and flash program memory are readable and writable during normal operation over the entire v dd range. a bulk erase operation may not be issued from user code (which includes removing code protection). the data memory is not directly mapped in the register file space. instead, it is indirectly addressed through the special function registers (sfr). there are six sfrs used to read and write the program and data eeprom memory. these registers are: ? eecon1 ? eecon2 ? eedata ? eedath ? eeadr ? eeadrh the eeprom data memory allows byte read and write. when interfacing to the data memory block, eedata holds the 8-bit data for read/write and eeadr holds the address of the eeprom location being accessed. the registers eedath and eeadrh are not used for data eeprom access. the pic16f872 device has 64 bytes of data eeprom with an address range from 0h to 3fh. the eeprom data memory is rated for high erase/ write cycles. the write time is controlled by an on-chip timer. the write time will vary with voltage and temper- ature, as well as from chip-to-chip. please refer to the specifications for exact limits. the program memory allows word reads and writes. program memory access allows for checksum calcula- tion and calibration table storage. a byte or word write automatically erases the location and writes the new data (erase before write). writing to program memory will cease operation until the write is complete. the pro- gram memory cannot be accessed during the write, therefore code cannot execute. during the write opera- tion, the oscillator continues to clock the peripherals, and therefore, they continue to operate. interrupt events will be detected and essentially queued until the write is completed. when the write completes, the next instruction in the pipeline is executed and the branch to the interrupt vector address will occur. when interfacing to the program memory block, the eedath:eedata registers form a two byte word, which holds the 14-bit data for read/write. the eeadrh:eeadr registers form a two byte word, which holds the 13-bit address of the flash location being accessed. the pic16f872 device has 2k words of program flash with an address range from 0h to 7ffh. the unused upper bits in both the eedath and eedata registers all read as 0s. the value written to program memory does not need to be a valid instruction. therefore, up to 14-bit numbers can be stored in memory for use as calibration param- eters, serial numbers, packed 7-bit ascii, etc. execut- ing a program memory location containing data that forms an invalid instruction results in a nop . 4.1 eeadr the address registers can address up to a maximum of 256 bytes of data eeprom or up to a maximum of 8k words of program flash. however, the pic16f872 has 64 bytes of data eeprom and 2k words of pro- gram flash. when selecting a program address value, the msbyte of the address is written to the eeadrh register and the lsbyte is written to the eeadr register. when selecting a data address value, only the lsbyte of the address is written to the eeadr register. on the pic16f872 device, the upper two bits of the eeadr must always be cleared to prevent inadvertent access to the wrong location in data eeprom. this also applies to the program memory. the upper five msbits of eeadrh must always be clear during pro- gram flash access. 4.2 eecon1 and eecon2 registers eecon1 is the control register for memory accesses. eecon2 is not a physical register. reading eecon2 will read all '0's. the eecon2 register is used exclusively in the memory write sequence. control bit eepgd determines if the access will be a program or a data memory access. when clear, any subsequent operations will operate on the data mem- ory. when set, any subsequent operations will operate on the program memory. control bits rd and wr initiate read and write opera- tions, respectively. these bits cannot be cleared, only set, in software. they are cleared in hardware at the completion of the read or write operation. the inability to clear the wr bit in software prevents the accidental or premature termination of a write operation. the wren bit, when set, will allow a write operation. on power-up, the wren bit is clear. the wrerr bit is set when a write operation is interrupted by a mclr reset or a wdt time-out reset during normal operation. in these situations, following reset, the user can check the wrerr bit and rewrite the location. the value of the data and address registers and the eepgd bit remains unchanged. interrupt flag bit eeif, in the pir2 register, is set when write is complete. it must be cleared in software.
pic16f872 ds30221a-page 30 preliminary ? 1999 microchip technology inc. register 4-1: eecon1 register (address 18ch) r/w-x u-0 u-0 u-0 r/w-x r/w-0 r/s-0 r/s-0 eepgd wrerr wren wr rd r = readable bit w = writable bit u = unimplemented bit, read as 0 - n= value at por reset bit7 bit0 bit 7: eepgd : program / data eeprom select bit 1 = accesses program memory 0 = accesses data memory (this bit cannot be changed while a read or write operation is in progress) bit 6-4: unimplemented: read as '0' bit 3: wrerr : eeprom error flag bit 1 = a write operation is prematurely terminated (any mclr reset or any wdt reset during normal operation) 0 = the write operation completed bit 2: wren : eeprom write enable bit 1 = allows write cycles 0 = inhibits write to the eeprom bit 1: wr : write control bit 1 = initiates a write cycle. (the bit is cleared by hardware once write is complete.) the wr bit can only be set (not cleared) in software. 0 = write cycle to the eeprom is complete bit 0: rd : read control bit 1 = initiates an eeprom read rd is cleared in hardware. the rd bit can only be set (not cleared) in software. 0 = does not initiate an eeprom read
? 1999 microchip technology inc. preliminary ds30221a-page 31 pic16f872 4.3 reading the data eeprom memory to read a data memory location, the user must write the address to the eeadr register, clear the eepgd con- trol bit (eecon1<7>) and then set control bit rd (eecon1<0>). the data is available in the very next instruction cycle of the eedata register, therefore it can be read by the next instruction. eedata will hold this value until another read operation or until it is writ- ten to by the user (during a write operation). example 4-1: data eeprom read bsf status, rp1 ; bcf status, rp0 ;bank 2 movlw data_ee_addr ; movwf eeadr ;data memory address to read bsf status, rp0 ;bank 3 bcf eecon1, eepgd ;point to data memory bsf eecon1, rd ;eeprom read bcf status, rp0 ;bank 2 movf eedata, w ;w = eedata 4.4 writing to the data eeprom memory to write an eeprom data location, the address must first be written to the eeadr register and the data writ- ten to the eedata register. then the sequence in example 4-2 must be followed to initiate the write cycle. example 4-2: data eeprom write the write will not initiate if the above sequence is not exactly followed (write 55h to eecon2, write aah to eecon2, then set wr bit) for each byte. it is strongly recommended that interrupts be disabled during this code segment. additionally, the wren bit in eecon1 must be set to enable writes. this mechanism prevents accidental writes to data eeprom due to unexpected code exe- cution (i.e., runaway programs). the wren bit should be kept clear at all times, except when updating the eeprom. the wren bit is not cleared by hardware after a write sequence has been initiated, clearing the wren bit will not affect the current write cycle. the wr bit will be inhibited from being set unless the wren bit is set. the wren bit must be set on a previous instruc- tion. both wr and wren cannot be set with the same instruction. at the completion of the write cycle, the wr bit is cleared in hardware and the eeprom write complete interrupt flag bit (eeif) is set. eeif must be cleared by software. bsf status, rp1 ; bcf status, rp0 ; bank 2 movlw data_ee_addr ; movwf eeadr ; data memory address to write movlw data_ee_data ; movwf eedata ; data memory value to write bsf status, rp0 ; bank 3 bcf eecon1, eepgd ; point to data memory bsf eecon1, wren ; enable writes bcf intcon, gie ; disable interrupts movlw 55h ; required movwf eecon2 ; write 55h sequence movlw aah ; movwf eecon2 ; write aah bsf eecon1, wr ; set wr bit to begin write bsf intcon, gie ; enable interrupts sleep ; wait for interrupt to signal write complete bcf eecon1, wren ; disable writes
pic16f872 ds30221a-page 32 preliminary ? 1999 microchip technology inc. 4.5 reading the flash program memory a program memory location may be read by writing two bytes of the address to the eeadr and eeadrh reg- isters, setting the eepgd control bit (eecon1<7>) and then setting control bit rd (eecon1<0>). once the read control bit is set, the microcontroller will use the next two instruction cycles to read the data. the data is available in the eedata and eedath registers after the second nop instruction. therefore, it can be read as two bytes in the following instructions. the eedata and eedath registers will hold this value until another read operation or until it is written to by the user (during a write operation). example 4-3: flash program read bsf status, rp1 ; bcf status, rp0 ; bank 2 movlw addrh ; movwf eeadrh ; msbyte of program address to read movlw addrl ; movwf eeadr ; lsbyte of program address to read bsf status, rp0 ; bank 3 bsf eecon1, eepgd ; point to program memory required bsf eecon1, rd ; eeprom read sequence nop ; memory is read in the next two cycles after bsf eecon1,rd nop ; bcf status, rp0 ; bank 2 movf eedata, w ; w = lsbyte of program eedata movf eedath, w ; w = msbyte of program eedata
? 1999 microchip technology inc. preliminary ds30221a-page 33 pic16f872 4.6 writing to the flash program memory when the pic16f872 is fully code protected or not code protected, a word of the flash program memory may be written provided the wrt configuration bit is set. if the pic16f872 is partially code protected, then a word of flash program memory may be written if the word is in a non-code protected segment of memory and the wrt configuration bit is set. to write a flash program location, the first two bytes of the address must be written to the eeadr and eeadrh registers and two bytes of the data to the eedata and eedath registers, set the eepgd control bit (eecon1<7>), and then set control bit wr (eecon1<1>). the sequence in example 4-4 must be followed to initiate a write to program memory. the microcontroller will then halt internal operations during the next two instruction cycles for the t pew (parameter d133) in which the write takes place. this is not sleep mode, as the clocks and peripherals will continue to run. therefore, the two instructions follow- ing the bsf eecon, wr should be nop instructions. after the write cycle, the microcontroller will resume operation with the 3rd instruction after the eecon1 write instruction. example 4-4: flash program write bsf status, rp1 ; bcf status, rp0 ; bank 2 movlw addrh ; movwf eeadrh ; msbyte of program address to read movlw addrl ; movwf eeadr ; lsbyte of program address to read movlw datah ; movwf eedath ; ms program memory value to write movlw datal ; movwf eedata ; ls program memory value to write bsf status, rp0 ; bank 3 bsf eecon1, eepgd ; point to program memory bsf eecon1, wren ; enable writes bcf intcon, gie ; disable interrupts movlw 55h ; required movwf eecon2 ; write 55h sequence movlw aah ; movwf eecon2 ; write aah bsf eecon1, wr ; set wr bit to begin write nop ; instructions here are ignored by the microcontroller nop ; microcontroller will halt operation and wait for ; a write complete. after the write ; the microcontroller continues with 3rd instruction bsf intcon, gie ; enable interrupts bcf eecon1, wren ; disable writes
pic16f872 ds30221a-page 34 preliminary ? 1999 microchip technology inc. 4.7 write verify depending on the application, good programming practice may dictate that the value written to the mem- ory should be verified against the original value. this should be used in applications where excessive writes can stress bits near the specification limit. generally a write failure will be a bit which was written as a '1', but reads back as a '0' (due to leakage off the bit). 4.8 protection against spurious write 4.8.1 eeprom data memory there are conditions when the device may not want to write to the data eeprom memory. to protect against spurious eeprom writes, various mechanisms have been built-in. on power-up, the wren bit is cleared. also, the power-up timer (72 ms duration) prevents eeprom write. the write initiate sequence and the wren bit together help prevent an accidental write during brown-out, power glitch, or software malfunction. 4.8.2 program flash memory to protect against spurious writes to flash program memory, the wrt bit in the configuration word may be programmed to 0 to prevent writes. the write initiate sequence must also be followed. wrt and the config- uration word cannot be programmed by user code, only through the use of an external programmer. 4.9 operation during code protect each reprogrammable memory block has its own code protect mechanism. external read and write opera- tions are disabled if either of these mechanisms are enabled. 4.9.1 data eeprom memory the microcontroller itself can both read and write to the internal data eeprom, regardless of the state of the code protect configuration bit. 4.9.2 program flash memory the microcontroller can read and execute instructions out of the internal flash program memory, regardless of the state of the code protect configuration bits. how- ever, the wrt configuration bit and the code protect bits have different effects on writing to program mem- ory. table 4-1 shows the various configurations and status of reads and writes. to erase the wrt or code protection bits in the configuration word requires that the device be fully erased. note: the pic16f872 devices can perform self writes to any location in program memory when not code protected or fully code protected. table 4-1: read/write state of internal flash program memory configuration bits memory location internal read internal write icsp read icsp write cp1 cp0 wrt 001 all program memory yes yes no no 000 all program memory yes no no no 010 unprotected areas yes no yes no 010 protected areas yes no no no 011 unprotected areas yes yes yes no 011 protected areas yes no no no 100 unprotected areas yes no yes no 100 protected areas yes no no no 101 unprotected areas yes yes yes no 101 protected areas yes no no no 110 all program memory yes no yes yes 111 all program memory yes yes yes yes
? 1999 microchip technology inc. preliminary ds30221a-page 35 pic16f872 table 4-2: registers associated with data eeprom/program flash addressnamebit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 value on: por, bor value on all other resets 0bh, 8bh, 10bh, 18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 10dh eeadr eeprom address register xxxx xxxx uuuu uuuu 10fh eeadrh eeprom address high xxxx xxxx uuuu uuuu 10ch eedata eeprom data resister xxxx xxxx uuuu uuuu 10eh eedath eeprom data resister high xxxx xxxx uuuu uuuu 18ch eecon1 eepgd wrerr wren wr rd x--- x000 x--- u000 18dh eecon2 eeprom control resister2 (not a physical resister) 8dh pie2 (1) eeie bclie (1) -r-0 0--r -r-0 0--r 0dh pir2 (1) eeif bclif (1) -r-0 0--r -r-0 0--r legend: x = unknown, u = unchanged, r = reserved, - = unimplemented read as '0'. shaded cells are not used by the timer1 module. note 1: these bits are reserved; always maintain these bits clear.
pic16f872 ds30221a-page 36 preliminary ? 1999 microchip technology inc. notes:
? 1999 microchip technology inc. preliminary ds30221a-page 37 pic16f872 5.0 timer0 module the timer0 module timer/counter has the following fea- tures: ? 8-bit timer/counter ? readable and writable ? 8-bit software programmable prescaler ? internal or external clock select ? interrupt on overflow from ffh to 00h ? edge select for external clock figure 5-1 is a block diagram of the timer0 module and the prescaler shared with the wdt. additional information on the timer0 module is avail- able in the picmicro? mid-range mcu family refer- ence manual (ds33023). timer mode is selected by clearing bit t0cs (option_reg<5>). in timer mode, the timer0 mod- ule will increment every instruction cycle (without pres- caler). if the tmr0 register is written, the increment is inhibited for the following two instruction cycles. the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting bit t0cs (option_reg<5>). in counter mode, timer0 will increment either on every rising or falling edge of pin ra4/t0cki. the incrementing edge is determined by the timer0 source edge select bit t0se (option_reg<4>). clearing bit t0se selects the ris- ing edge. restrictions on the external clock input are discussed in detail in section 5.2. the prescaler is mutually exclusively shared between the timer0 module and the watchdog timer. the pres- caler is not readable or writable. section 5.3 details the operation of the prescaler. 5.1 timer0 interrupt the tmr0 interrupt is generated when the tmr0 reg- ister overflows from ffh to 00h. this overflow sets bit t0if (intcon<2>). the interrupt can be masked by clearing bit t0ie (intcon<5>). bit t0if must be cleared in software by the timer0 module interrupt ser- vice routine before re-enabling this interrupt. the tmr0 interrupt cannot awaken the processor from sleep since the timer is shut off during sleep. figure 5-1: block diagram of the timer0/wdt prescaler ra4/t0cki t0se pin m u x clkout (= f osc /4) sync 2 cycles tmr0 reg 8-bit prescaler 8 - to - 1mux m u x m u x watchdog timer psa 0 1 0 1 wdt time-out ps<2:0> 8 note: t0cs, t0se, psa, ps<2:0> are (option_reg<5:0>). psa wdt enable bit m u x 0 1 0 1 data bus set flag bit t0if on overflow 8 psa t0cs prescaler
pic16f872 ds30221a-page 38 preliminary ? 1999 microchip technology inc. 5.2 using timer0 with an external clock when no prescaler is used, the external clock input is the same as the prescaler output. the synchronization of t0cki with the internal phase clocks is accom- plished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks. therefore, it is necessary for t0cki to be high for at least 2t osc (and a small rc delay of 20 ns) and low for at least 2t osc (and a small rc delay of 20 ns). refer to the electrical specification of the desired device. 5.3 pre scaler there is only one prescaler available, which is mutually exclusively shared between the timer0 module and the watchdog timer. a prescaler assignment for the timer0 module means that there is no prescaler for the watch- dog timer, and vice-versa. this prescaler is not readable or writable (see figure 5-1). the psa and ps<2:0> bits (option_reg<3:0>) deter- mine the prescaler assignment and prescale ratio. when assigned to the timer0 module, all instructions writing to the tmr0 register (i.e., clrf 1, movwf 1, bsf 1,x ...., etc.) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the watchdog timer. the pres- caler is not readable or writable. register 5-1: option_reg register note: writing to tmr0, when the prescaler is assigned to timer0, will clear the prescaler count, but will not change the prescaler assignment. r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbp u intedg t0cs t0se psa ps2 ps1 ps0 r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit 7 bit 0 bit 7: rbpu bit 6: intedg bit 5: t0cs : tmr0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (clkout) bit 4: t0se : tmr0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3: psa : prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0: ps<2:0> : prescaler rate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate note: to avoid an unintended device reset, the instruction sequence shown in the picmicro? mid-range mcu family reference manual (ds33023) must be executed when changing the prescaler assignment from timer0 to the wdt. this sequence must be followed even if the wdt is disabled.
? 1999 microchip technology inc. preliminary ds30221a-page 39 pic16f872 table 5-1: registers associated with timer0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 01h,101h tmr0 timer0 modules register xxxx xxxx uuuu uuuu 0bh,8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 81h,181h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by timer0.
pic16f872 ds30221a-page 40 preliminary ? 1999 microchip technology inc. notes:
? 1999 microchip technology inc. preliminary ds30221a-page 41 pic16f872 6.0 timer1 module the timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (tmr1h and tmr1l), which are readable and writable. the tmr1 register pair (tmr1h:tmr1l) increments from 0000h to ffffh and rolls over to 0000h. the tmr1 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit tmr1if (pir1<0>). this interrupt can be enabled/disabled by setting/clearing tmr1 interrupt enable bit tmr1ie (pie1<0>). timer1 can operate in one of two modes: ?as a timer ?as a counter the operating mode is determined by the clock select bit, tmr1cs (t1con<1>). in timer mode, timer1 increments every instruction cycle. in counter mode, it increments on every rising edge of the external clock input. timer1 can be enabled/disabled by setting/clearing control bit tmr1on (t1con<0>). timer1 also has an internal reset input. this reset can be generated by the ccp module (section 8.0). register 6-1 shows the timer1 control register. when the timer1 oscillator is enabled (t1oscen is set), the rc1/t1osi and rc0/t1oso/t1cki pins become inputs. that is, the trisc<1:0> value is ignored. additional information on timer modules is available in the picmicro? mid-range mcu family reference manual (ds33023). register 6-1: t1con: timer1 control register (address 10h) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7-6: unimplemented: read as '0' bit 5-4: t1ckps<1:0> : timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3: t1oscen : timer1 oscillator enable control bit 1 = oscillator is enabled 0 = oscillator is shut off (the oscillator inverter is turned off to eliminate power drain) bit 2: t1sync : timer1 external clock input synchronization control bit t mr1cs = 1 1 = do not synchronize external clock input 0 = synchronize external clock input t mr1cs = 0 this bit is ignored. timer1 uses the internal clock when tmr1cs = 0. bit 1: tmr1cs : timer1 clock source select bit 1 = external clock from pin rc0/t1oso/t1cki (on the rising edge) 0 = internal clock (f osc /4) bit 0: tmr1on : timer1 on bit 1 = enables timer1 0 = stops timer1
pic16f872 ds30221a-page 42 preliminary ? 1999 microchip technology inc. 6.1 timer1 operation in timer mode timer mode is selected by clearing the tmr1cs (t1con<1>) bit. in this mode, the input clock to the timer is f osc /4. the synchronize control bit t1sync (t1con<2>) has no effect since the internal clock is always in sync. 6.2 t imer1 counter operation timer1 may operate in asynchronous or usynchronous mode depending on the setting of the tmr1cs bit. when timer1 is being incremented via an external source, increments occur on a rising edge. after timer1 is enabled in counter mode, the module must first have a falling edge before the counter begins to increment. figure 6-1: timer1 incrementing edge 6.3 timer1 operation in synchronized counter mode counter mode is selected by setting bit tmr1cs. in this mode, the timer increments on every rising edge of clock input on pin rc1/t1osi, when bit t1oscen is set, or on pin rc0/t1oso/t1cki, when bit t1oscen is cleared. if t1sync is cleared, then the external clock input is synchronized with internal phase clocks. the synchro- nization is done after the prescaler stage. the pres- caler stage is an asynchronous ripple-counter. in this configuration, during sleep mode, timer1 will not increment even if the external clock is present, since the synchronization circuit is shut off. the pres- caler however will continue to increment. figure 6-2: timer1 block diagram t1cki (default high) t1cki (default low) note: arrows indicate counter increments. tmr1h tmr1l t1osc t1sync tmr1cs t1ckps<1:0> q clock t1oscen enable oscillator (1) f osc /4 internal clock tmr1on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 rc0/t1oso/t1cki rc1/t1osi (2) note 1: when the t1oscen bit is cleared, the inverter is turned off. this eliminates power drain. 2: for the pic16f872, the schmitt trigger is not implemented in external clock mode. set flag bit tmr1if on overflow tmr1 (2)
? 1999 microchip technology inc. preliminary ds30221a-page 43 pic16f872 6.4 timer1 operation in asynchronous counter mode if control bit t1sync (t1con<2>) is set, the external clock input is not synchronized. the timer continues to increment asynchronous to the internal phase clocks. the timer will continue to run during sleep and can generate an interrupt on overflow, which will wake-up the processor. however, special precautions in soft- ware are needed to read/write the timer (section 6.4.1). in asynchronous counter mode, timer1 can not be used as a time-base for capture or compare operations. 6.4.1 reading and writing timer1 in asynchronous counter mode reading tmr1h or tmr1l while the timer is running from an external asynchronous clock will guarantee a valid read (taken care of in hardware). however, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself poses certain problems, since the timer may overflow between the reads. for writes, it is recommended that the user simply stop the timer and write the desired values. a write conten- tion may occur by writing to the timer registers, while the register is incrementing. this may produce an unpredictable value in the timer register. reading the 16-bit value requires some care. examples 12-2 and 12-3 in the picmicro ? mid-range mcu fam- ily reference manual (ds33023) show how to read and write timer1 when it is running in asynchronous mode. 6.5 timer1 oscillator a crystal oscillator circuit is built-in between pins t1osi (input) and t1oso (amplifier output). it is enabled by setting control bit t1oscen (t1con<3>). the oscilla- tor is a low power oscillator rated up to 200 khz. it will continue to run during sleep. it is primarily intended for use with a 32 khz crystal. table 6-1 shows the capacitor selection for the timer1 oscillator. the timer1 oscillator is identical to the lp oscillator. the user must provide a software time delay to ensure proper oscillator start-up. table 6-1: capacitor selection for the timer1 oscillator 6.6 resetting timer1 using ccp 1 trigger output if the ccp1 module is configured in compare mode to generate a special event trigger (ccp1m<3:0> = 1011 ), this signal will reset timer1. timer1 must be configured for either timer or synchro- nized counter mode to take advantage of this feature. if timer1 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer1 coincides with a spe- cial event trigger from ccp1, the write will take prece- dence. in this mode of operation, the ccpr1h:ccpr1l regis- ter pair effectively becomes the period register for timer1. 6.7 resetting of timer1 register pair (tmr1h, tmr1l) tmr1h and tmr1l registers are not reset to 00h on a por or any other reset except by the ccp1 special event trigger. t1con register is reset to 00h on a power-on reset or a brown-out reset, which shuts off the timer and leaves a 1:1 prescale. in all other resets, the register is unaffected. 6.8 timer1 prescaler the prescaler counter is cleared on writes to the tmr1h or tmr1l registers. osc type freq c1 c2 lp 32 khz 33 pf 33 pf 100 khz 15 pf 15 pf 200 khz 15 pf 15 pf these values are for design guidance only. crystals tested: 32.768 khz epson c-001r32.768k-a 20 ppm 100 khz epson c-2 100.00 kc-p 20 ppm 200 khz std xtl 200.000 khz 20 ppm note 1: higher capacitance increases the stability of oscillator, but also increases the start-up time. 2: since each resonator/crystal has its own charac- teristics, the user should consult the resonator/ crystal manufacturer for appropriate values of external components. note: the special event trigger from the ccp1 module will not set interrupt flag bit tmr1if (pir1<0>).
pic16f872 ds30221a-page 44 preliminary ? 1999 microchip technology inc. table 6-2: registers associated with timer1 as a timer/counter addressnamebit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 value on: por, bor value on all other resets 0bh, 8bh, 10bh, 18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 (1) adif (1) (1) sspif ccp1if tmr2if tmr1if r0rr 0000 r0rr 0000 8ch pie1 (1) adie (1) (1) sspie ccp1ie tmr2ie tmr1ie r0rr 0000 r0rr 0000 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu legend: x = unknown, u = unchanged, r = reserved, - = unimplemented read as '0'. shaded cells are not used by the timer1 module. note 1: these bits are reserved; always maintain these bits clear.
? 1999 microchip technology inc. preliminary ds30221a-page 45 pic16f872 7.0 timer2 module timer2 is an 8-bit timer with a prescaler and a postscaler. it can be used as the pwm time-base for the pwm mode of the ccp module. the tmr2 register is readable and writable, and is cleared on any device reset. the input clock (f osc /4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits t2ckps<1:0> (t2con<1:0>). the timer2 module has an 8-bit period register pr2. timer2 increments from 00h until it matches pr2 and then resets to 00h on the next increment cycle. pr2 is a readable and writable register. the pr2 register is initialized to ffh upon reset. the match output of tmr2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a tmr2 interrupt (latched in flag bit tmr2if, (pir1<1>)). timer2 can be shut off by clearing control bit tmr2on (t2con<2>) to minimize power consumption. register 7-1 shows the timer2 control register. additional information on timer modules is available in the picmicro? mid-range mcu family reference manual (ds33023). 7.1 timer2 prescaler and postscaler the prescaler and postscaler counters are cleared when any of the following occurs: ? a write to the tmr2 register ? a write to the t2con register ? any device reset (por, mclr reset, wdt reset or bor) tmr2 is not cleared when t2con is written. 7.2 output of tmr2 the output of tmr2 (before the postscaler) is fed to the ssport module, which optionally uses it to generate shift clock. figure 7-1: timer2 block diagram register 7-1: t2con: timer2 control register (address 12h) comparator tmr2 sets flag tmr2 reg output (1) reset postscaler prescaler pr2 reg 2 f osc /4 1:1 1:16 1:1, 1:4, 1:16 eq 4 bit tmr2if note 1: tmr2 register output can be software selected by the ssp module as a baud clock. to t2outps<3:0> t2ckps<1:0> u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7: unimplemented: read as '0' bit 6-3: toutps<3:0> : timer2 output postscale select bits 0000 = 1:1 postscale 0001 = 1:2 postscale 0010 = 1:3 postscale ? ? ? 1111 = 1:16 postscale bit 2: tmr2on : timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0: t2ckps<1:0> : timer2 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16
pic16f872 ds30221a-page 46 preliminary ? 1999 microchip technology inc. table 7-1: registers associated with timer2 as a timer/counter address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 (1) adif (1) (1) sspif ccp1if tmr2if tmr1if r0rr 0000 r0rr 0000 8ch pie1 (1) adie (1) (1) sspie ccp1ie tmr2ie tmr1ie r0rr 0000 r0rr 0000 11h tmr2 timer2 modules register 0000 0000 0000 0000 12h t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 92h pr2 timer2 period register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, r = reserved, - = unimplemented read as '0'. shaded cells are not used by the timer2 module. note 1: these bits are reserved; always maintain these bits clear.
? 1999 microchip technology inc. preliminary ds30221a-page 47 pic16f872 8.0 capture/compare/pwm module the capture/compare/pwm (ccp) module contains a 16-bit register which can operate as a: ? 16-bit capture register ? 16-bit compare register ? pwm master/slave duty cycle register ta bl e 8 - 1 shows the resources used by the ccp mod- ule. in the following sections, the operation of a ccp module is described. ccp1 module: capture/compare/pwm register1 (ccpr1) is com- prised of two 8-bit registers: ccpr1l (low byte) and ccpr1h (high byte). the ccp1con register controls the operation of ccp1. the special event trigger is generated by a compare match and will reset timer1 and start an a/d conversion (if the a/d module is enabled). additional information on ccp modules is available in the picmicro? mid-range mcu family reference manual (ds33023) and in application note 594, using the ccp modules (ds00594). table 8-1: ccp mode - timer resources required register 8-1: ccp1con register (address: 17h) ccp mode timer resource capture compare pwm timer1 timer1 timer2 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7-6: unimplemented: read as '0' bit 5-4: ccp1 : pwm least significant bits capture mode: unused compare mode: unused pwm mode: these bits are the two lsbs of the pwm duty cycle. the eight msbs are found in ccpr1l. bit 3-0: ccp1m<3:0> : ccpx mode select bits 0000 = capture/compare/pwm off (resets ccp module) 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode, set output on match (ccp1if bit is set) 1001 = compare mode, clear output on match (ccp1if bit is set) 1010 = compare mode, generate software interrupt on match (ccp1if bit is set, ccp pin is unaffected) 1011 = compare mode, trigger special event (ccp1if bit is set, ccp1 pin is unaffected); ccp1 resets tmr1 and starts an a/d conversion (if a/d module is enabled) 11xx = pwm mode
pic16f872 ds30221a-page 48 preliminary ? 1999 microchip technology inc. 8.1 capture mode in capture mode, ccpr1h:ccpr1l captures the 16-bit value of the tmr1 register when an event occurs on pin rc2/ccp1. an event is defined as: ? every falling edge ? every rising edge ? every 4th rising edge ? every 16th rising edge an event is selected by control bits ccp1m<3:0> (ccp1con<3:0>). when a capture is made, the inter- rupt request flag bit ccp1if (pir1<2>) is set. the interrupt flag must be cleared in software. if another capture occurs before the value in register ccpr1 is read, the old captured value will be lost. 8.1.1 ccp pin configuration in capture mode, the rc2/ccp1 pin should be config- ured as an input by setting the trisc<2> bit. figure 8-1: capture mode operation block diagram 8.1.2 timer1 mode selection timer1 must be running in timer mode or synchronized counter mode for the ccp module to use the capture feature. in asynchronous counter mode, the capture operation may not work. 8.1.3 software interrupt when the capture mode is changed, a false capture interrupt may be generated. the user should keep bit ccp1ie (pie1<2>) clear to avoid false interrupts and should clear the flag bit ccp1if following any such change in operating mode. 8.1.4 ccp prescaler there are four prescaler settings, specified by bits ccp1m<3:0>. whenever the ccp module is turned off, or the ccp module is not in capture mode, the pres- caler counter is cleared. any reset will clear the pres- caler counter. switching from one capture prescaler to another may generate an interrupt. also, the prescaler counter will not be cleared, therefore, the first capture may be from a non-zero prescaler. example 8-1 shows the recom- mended method for switching between capture pres- calers. this example also clears the prescaler counter and will not generate the false interrupt. example 8-1: changing between capture prescalers clrf ccp1con ;turn ccp module off movlw new_capt_ps ;load the w reg with ; the new precscaler ; move value and ccp on movwf ccp1con ;load ccp1con with this ; value note: if the rc2/ccp1 pin is configured as an output, a write to the port can cause a cap- ture condition. ccpr1h ccpr1l tmr1h tmr1l set flag bit ccp1if (pir1<2>) capture enable qs ccp1con<3:0> rc2/ccp1 prescaler ? 1, 4, 16 and edge detect pin
? 1999 microchip technology inc. preliminary ds30221a-page 49 pic16f872 8.2 compare mode in compare mode, the 16-bit ccpr1 register value is constantly compared against the tmr1 register pair value. when a match occurs, the rc2/ccp1 pin is: ? driven high ?driven low ? remains unchanged the action on the pin is based on the value of control bits ccp1m<3:0> (ccp1con<3:0>). at the same time, interrupt flag bit ccp1if is set. figure 8-2: compare mode operation block diagram 8.2.1 ccp pin configuration the user must configure the rc2/ccp1 pin as an out- put by clearing the trisc<2> bit. 8.2.2 timer1 mode selection timer1 must be running in timer mode or synchro- nized counter mode if the ccp module is using the compare feature. in asynchronous counter mode, the compare operation may not work. 8.2.3 software interrupt mode when generate software interrupt mode is chosen, the ccp1 pin is not affected. the ccpif bit is set causing a ccp interrupt (if enabled). 8.2.4 special event trigger in this mode, an internal hardware trigger is generated, which may be used to initiate an action. the special event trigger output of ccp1 resets the tmr1 register pair and starts an a/d conversion (if the a/d module is enabled). this allows the ccpr1 regis- ter to effectively be a 16-bit programmable period reg- ister for timer1. . 8.3 pwm mode (pwm) in pulse width modulation mode, the ccp1 pin pro- duces up to a 10-bit resolution pwm output. since the ccp1 pin is multiplexed with the portc data latch, the trisc<2> bit must be cleared to make the ccp1 pin an output. figure 8-3 shows a simplified block diagram of the ccp module in pwm mode. for a step-by-step procedure on how to set up the ccp module for pwm operation, see section 8.3.3 . figure 8-3: simplified pwm block diagram note: clearing the ccp1con register will force the rc2/ccp1 compare output latch to the default low level. this is not the data latch. ccpr1h ccpr1l tmr1h tmr1l comparator qs r output logic special event trigger set flag bit ccp1if (pir1<2>) match rc2/ccp1 trisc<2> ccp1con<3:0> mode select output enable pin special event trigger will: reset timer1, but not set interrupt flag bit tmr1if (pir1<0>), and set bit go/done (adcon0<2>). note: the special event trigger from the ccp1 module will not set interrupt flag bit tmr1if (pir1<0>). note: clearing the ccp1con register will force the ccp1 pwm output latch to the default low level. this is not the portc i/o data latch. ccpr1l ccpr1h (slave) comparator tmr2 comparator pr2 (note 1) r q s duty cycle registers ccp1con<5:4> clear timer, ccp1 pin and latch d.c. trisc<2> rc2/ccp1 note 1: 8-bit timer is concatenated with 2-bit internal q clock or 2 bits of the prescaler to create 10-bit time-base.
pic16f872 ds30221a-page 50 preliminary ? 1999 microchip technology inc. a pwm output ( figure 8-4 ) has a time-base (period) and a time that the output stays high (duty cycle). the frequency of the pwm is the inverse of the period (1/period). figure 8-4: pwm output 8.3.1 pwm period the pwm period is specified by writing to the pr2 reg- ister. the pwm period can be calculated using the fol- lowing formula: pwm period = [(pr2) + 1] ? 4 ? t osc ? (tmr2 prescale value) pwm frequency is defined as 1 / [pwm period]. when tmr2 is equal to pr2, the following three events occur on the next increment cycle: ? tmr2 is cleared ? the ccp1 pin is set (exception: if pwm duty cycle = 0%, the ccp1 pin will not be set) ? the pwm duty cycle is latched from ccpr1l into ccpr1h 8.3.2 pwm duty cycle the pwm duty cycle is specified by writing to the ccpr1l register and to the ccp1con<5:4> bits. up to 10-bit resolution is available. the ccpr1l contains the eight msbs and the ccp1con<5:4> contains the two lsbs. this 10-bit value is represented by ccpr1l:ccp1con<5:4>. the following equation is used to calculate the pwm duty cycle in time: pwm duty cycle = (ccpr1l:ccp1con<5:4>) ? tosc ? (tmr2 prescale value) ccpr1l and ccp1con<5:4> can be written to at any time, but the duty cycle value is not latched into ccpr1h until after a match between pr2 and tmr2 occurs (i.e., the period is complete). in pwm mode, ccpr1h is a read-only register. the ccpr1h register and a 2-bit internal latch are used to double buffer the pwm duty cycle. this double buffering is essential for glitchless pwm operation. when the ccpr1h and 2-bit latch match tmr2 con- catenated with an internal 2-bit q clock or 2 bits of the tmr2 prescaler, the ccp1 pin is cleared. maximum pwm resolution (bits) for a given pwm frequency: 8.3.3 set-up for pwm operation the following steps should be taken when configuring the ccp module for pwm operation: 1. set the pwm period by writing to the pr2 register. 2. set the pwm duty cycle by writing to the ccpr1l register and ccp1con<5:4> bits. 3. make the ccp1 pin an output by clearing the trisc<2> bit. 4. set the tmr2 prescale value and enable timer2 by writing to t2con. 5. configure the ccp1 module for pwm operation. note: the timer2 postscaler (see section 8.1 ) is not used in the determination of the pwm frequency. the postscaler could be used to have a servo update rate at a different fre- quency than the pwm output. period duty cycle tmr2 = pr2 tmr2 = duty cycle tmr2 = pr2 note: if the pwm duty cycle value is longer than the pwm period, the ccp1 pin will not be cleared. log ( f pwm log(2) f osc ) bits = resolution
? 1999 microchip technology inc. preliminary ds30221a-page 51 pic16f872 table 8-2: registers associated with capture, compare and timer1 table 8-3: registers associated with pwm and timer2 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 (1) adif (1) (1) sspif ccp1if tmr2if tmr1if r0rr 0000 r0rr 0000 8ch pie1 (1) adie (1) (1) sspie ccp1ie tmr2ie tmr1ie r0rr 0000 r0rr 0000 87h trisc portc data direction register 1111 1111 1111 1111 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu 15h ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, r = reserved, - = unimplemented read as '0'. shaded cells are not used by capture and timer1. note 1: these bits are reserved; always maintain these bits clear. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 (1) adif (1) (1) sspif ccp1if tmr2if tmr1if r0rr 0000 r0rr 0000 8ch pie1 (1) adie (1) (1) sspie ccp1ie tmr2ie tmr1ie r0rr 0000 r0rr 0000 87h trisc portc data direction register 1111 1111 1111 1111 11h tmr2 timer2 modules register 0000 0000 0000 0000 92h pr2 timer2 modules period register 1111 1111 1111 1111 12h t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 15h ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, r = reserved, - = unimplemented read as '0'. shaded cells are not used by pwm and timer2. note 1: these bits are reserved; always maintain these bits clear.
pic16f872 ds30221a-page 52 preliminary ? 1999 microchip technology inc. notes:
? 1999 microchip technology inc. preliminary ds30221a-page 53 pic16f872 9.0 master synchronous serial port (mssp) module the master synchronous serial port (mssp) module is a serial interface useful for communicating with other peripheral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, dis- play drivers, a/d converters, etc. the mssp module can operate in one of two modes: ? serial peripheral interface (spi) ? inter-integrated circuit (i 2 c) figure 9-1 shows a block diagram for the spi mode, while figure 9-5 and figure 9-9 show the block dia- grams for the two different i 2 c modes of operation.
pic16f872 ds30221a-page 54 preliminary ? 1999 microchip technology inc. register 9-1: sspstat: sync serial port status register (address: 94h) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a psr/w ua bf r = readable bit w = writable bit u = unimplemented bit, read as 0 - n= value at por reset bit7 bit0 bit 7: smp : sample bit spi master mode 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time spi slave mode smp must be cleared when spi is used in slave mode in i 2 c master or slave mode: 1 = slew rate control disabled for standard speed mode (100 khz and 1 mhz) 0 = slew rate control enabled for high speed mode (400 khz) bit 6: cke : spi clock edge select ( figure 9-4 , figure 9-5 and figure 9-6 ) spi mode: ckp = 0 1 = transmit happens on transition from active clock state to idle clock state 0 = transmit happens on transition from idle clock state to active clock state ckp = 1 1 = data transmitted on falling edge of sck 0 = data transmitted on rising edge of sck in i 2 c master or slave mode: 1 = input levels conform to smbus spec 0 = input levels conform to i 2 c specs bit 5: d/a : data/address bit (i 2 c mode only) 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4: p : stop bit (i 2 c mode only. this bit is cleared when the mssp module is disabled, sspen is cleared.) 1 = indicates that a stop bit has been detected last (this bit is '0' on reset) 0 = stop bit was not detected last bit 3: s : start bit (i 2 c mode only. this bit is cleared when the mssp module is disabled, sspen is cleared.) 1 = indicates that a start bit has been detected last (this bit is '0' on reset) 0 = start bit was not detected last bit 2: r/w : read/write bit information (i 2 c mode only) this bit holds the r/w bit information following the last address match. this bit is only valid from the address match to the next start bit, stop bit or not ack bit. in i 2 c slave mode: 1 = read 0 = write in i 2 c master mode: 1 = transmit is in progress 0 = transmit is not in progress. oring this bit with sen, rsen, pen, rcen or acken will indicate if the mssp is in idle mode. bit 1: ua : update address (10-bit i 2 c mode only) 1 = indicates that the user needs to update the address in the sspadd register 0 = address does not need to be updated bit 0: bf : buffer full status bit receive (spi and i 2 c modes) 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty tr a n s m i t ( i 2 c mode only) 1 = data transmit in progress (does not include the ack and stop bits), sspbuf is full 0 = data transmit complete (does not include the ack and stop bits), sspbuf is empty
? 1999 microchip technology inc. preliminary ds30221a-page 55 pic16f872 register 9-2: sspcon: sync serial port control register (address 14h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 r = readable bit w = writable bit u = unimplemented bit, read as 0 - n= value at por reset bit7 bit0 bit 7: wcol : write collision detect bit master mode: 1 = a write to sspbuf was attempted while the i 2 c conditions were not valid 0 = no collision slave mode: 1 = sspbuf register is written while still transmitting the previous word (must be cleared in software) 0 = no collision bit 6: sspov : receive overflow indicator bit in spi mode 1 = a new byte is received while sspbuf holds previous data. data in sspsr is lost on overflow. in slave mode, the user must read the sspbuf, even if only transmitting data to avoid overflows. in master mode, the overflow bit is not set since each operation is initiated by writing to the sspbuf register. (must be cleared in software.) 0 = no overflow in i 2 c mode 1 = a byte is received while the sspbuf is holding the previous byte. sspov is a "dont care" in transmit mode. (must be cleared in software.) 0 = no overflow bit 5: sspen : synchronous serial port enable bit in spi mode , when enabled, these pins must be properly configured as input or output. 1 = enables serial port and configures sck, sdo, sdi, and ss as the source of the serial port pins 0 = disables serial port and configures these pins as i/o port pins in i 2 c mode , when enabled, these pins must be properly configured as input or output. 1 = enables the serial port and configures the sda and scl pins as the source of the serial port pins 0 = disables serial port and configures these pins as i/o port pins bit 4: ckp : clock polarity select bit in spi mode 1 = idle state for clock is a high level 0 = idle state for clock is a low level in i 2 c slave mode , sck release control 1 = enable clock 0 = holds clock low (clock stretch) (used to ensure data setup time) in i 2 c master mode unused in this mode bit 3-0: sspm<3:0> : synchronous serial port mode select bits 0000 = spi master mode, clock = f osc /4 0001 = spi master mode, clock = f osc /16 0010 = spi master mode, clock = f osc /64 0011 = spi master mode, clock = tmr2 output/2 0100 = spi slave mode, clock = sck pin. ss pin control enabled. 0101 = spi slave mode, clock = sck pin. ss pin control disabled. ss can be used as i/o pin. 0110 = i 2 c slave mode, 7-bit address 0111 = i 2 c slave mode, 10-bit address 1000 = i 2 c master mode, clock = f osc / (4 * (sspadd+1) ) 1011 = i 2 c firmware controlled master mode (slave idle) 1110 = i 2 c firmware controlled master mode, 7-bit address with start and stop bit interrupts enabled. 1111 = i 2 c firmware controlled master mode, 10-bit address with start and stop bit interrupts enabled. 1001, 1010, 1100, 1101 = reserved
pic16f872 ds30221a-page 56 preliminary ? 1999 microchip technology inc. register 9-3: sspcon2: sync serial port control register2 (address 91h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gcen ackstat ackdt acken rcen pen rsen sen r = readable bit w= writable bit u = unimplemented bit, read as 0 - n= value at por reset bit7 bit0 bit 7: gcen : general call enable bit (in i 2 c slave mode only) 1 = enable interrupt when a general call address (0000h) is received in the sspsr. 0 = general call address disabled. bit 6: ackstat : acknowledge status bit (in i 2 c master mode only) in master transmit mode: 1 = acknowledge was not received from slave. 0 = acknowledge was received from slave. bit 5: ackdt : acknowledge data bit (in i 2 c master mode only) in master receive mode: value that will be transmitted when the user initiates an acknowledge sequence at the end of a receive. 1 = not acknowledge. 0 = acknowledge. bit 4: acken : acknowledge sequence enable bit (in i 2 c master mode only). in master receive mode: 1 = initiate acknowledge sequence on sda and scl pins, and transmit ackdt data bit. automatically cleared by hardware. 0 = acknowledge sequence idle. bit 3: rcen : receive enable bit (in i 2 c master mode only). 1 = enables receive mode for i 2 c. 0 = receive idle. bit 2: pen : stop condition enable bit (in i 2 c master mode only). sck release control 1 = initiate stop condition on sda and scl pins. automatically cleared by hardware. 0 = stop condition idle. bit 1: rsen : repeated start condition enabled bit (in i 2 c master mode only) 1 = initiate repeated start condition on sda and scl pins. automatically cleared by hardware. 0 = repeated start condition idle. bit 0: sen : start condition enabled bit (in i 2 c master mode only) 1 = initiate start condition on sda and scl pins. automatically cleared by hardware. 0 = start condition idle. note: for bits acken, rcen, pen, rsen, sen: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling), and the sspbuf may not be written (or writes to the sspbuf are disabled).
? 1999 microchip technology inc. preliminary ds30221a-page 57 pic16f872 9.1 spi mode the spi mode allows 8 bits of data to be synchronously transmitted and received simultaneously. all four modes of spi are supported. to accomplish communi- cation, typically three pins are used: ? serial data out (sdo) ? serial data in (sdi) ? serial clock (sck) additionally, a fourth pin may be used when in a slave mode of operation: ?slave select (ss ) when initializing the spi, several options need to be specified. this is done by programming the appropriate control bits (sspcon<5:0> and sspstat<7:6>). these control bits allow the following to be specified: ? master mode (sck is the clock output) ? slave mode (sck is the clock input) ? clock polarity (idle state of sck) ? data input sample phase (middle or end of data output time) ? clock edge (output data on rising/falling edge of sck) ? clock rate (master mode only) ? slave select mode (slave mode only) figure 9-4 shows the block diagram of the mssp mod- ule when in spi mode. figure 9-1: mssp block diagram (spi mode) to enable the serial port, mssp enable bit, sspen (sspcon<5>) must be set. to reset or reconfigure spi mode, clear bit sspen, re-initialize the sspcon reg- isters, and then set bit sspen. this configures the sdi, sdo, sck and ss pins as serial port pins. for the pins to behave as the serial port function, some must have their data direction bits (in the tris register) appropriately programmed. that is: ? sdi is automatically controlled by the spi module ? sdo must have trisc<5> cleared ? sck (master mode) must have trisc<3> cleared ? sck (slave mode) must have trisc<3> set ?ss must have trisa<5> set any serial port function that is not desired may be over- ridden by programming the corresponding data direc- tion (tris) register to the opposite value. read write internal data bus sspsr reg sspbuf reg sspm3:sspm0 bit0 shift clock ss control enable edge select clock select tmr2 output t osc prescaler 4, 16, 64 2 edge select 2 4 data to tx/rx in sspsr data direction bit 2 smp:cke sdi sdo ss sck
pic16f872 ds30221a-page 58 preliminary ? 1999 microchip technology inc. 9.1.1 master mode the master can initiate the data transfer at any time because it controls the sck. the master determines when the slave (processor 2, figure 9-5 ) is to broad- cast data by the software protocol. in master mode, the data is transmitted/received as soon as the sspbuf register is written to. if the spi module is only going to receive, the sdo output could be disabled (programmed as an input). the sspsr register will continue to shift in the signal present on the sdi pin at the programmed clock rate. as each byte is received, it will be loaded into the sspbuf register as if a normal received byte (interrupts and status bits appropriately set). this could be useful in receiver applications as a line activity monitor. the clock polarity is selected by appropriately program- ming bit ckp (sspcon<4>). this then would give waveforms for spi communication as shown in figure 9-6 , figure 9-8 and figure 9-9 where the msb is transmitted first. in master mode, the spi clock rate (bit rate) is user programmable to be one of the following: ?f osc /4 (or t cy ) ?f osc /16 (or 4 ? t cy ) ?f osc /64 (or 16 ? t cy ) ? timer2 output/2 this allows a maximum bit clock frequency (at 20 mhz) of 5.0 mhz. figure 9-6 shows the waveforms for master mode. when cke = 1, the sdo data is valid before there is a clock edge on sck. the change of the input sample is shown based on the state of the smp bit. the time when the sspbuf is loaded with the received data is shown. figure 9-2: spi mode timing, master mode sck (ckp = 0, sdi (smp = 0) sspif bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sdi (smp = 1) sck (ckp = 0, sck (ckp = 1, sck (ckp = 1, sdo bit7 bit7 bit0 bit0 cke = 0) cke = 1) cke = 0) cke = 1)
? 1999 microchip technology inc. preliminary ds30221a-page 59 pic16f872 9.1.2 slave mode in slave mode, the data is transmitted and received as the external clock pulses appear on sck. when the last bit is latched, the interrupt flag bit sspif (pir1<3>) is set. while in slave mode, the external clock is supplied by the external clock source on the sck pin. this external clock must meet the minimum high and low times as specified in the electrical specifications. while in sleep mode, the slave can transmit/receive data. when a byte is received, the device will wake-up from sleep. figure 9-3: spi mode timing (slave mode with cke = 0) figure 9-4: spi mode timing (slave mode with cke = 1) note: when the spi module is in slave mode with ss pin control enabled, (ssp- con<3:0> = 0100 ) the spi module will reset if the ss pin is set to v dd . note: if the spi is used in slave mode with cke = '1', then ss pin control must be enabled. sck (ckp = 0) sdi (smp = 0) sspif bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sck (ckp = 1) sdo bit7 bit0 ss (optional) sck (ckp = 0) sdi (smp = 0) sspif bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sck (ckp = 1) sdo bit7 bit0 ss
pic16f872 ds30221a-page 60 preliminary ? 1999 microchip technology inc. table 9-1 registers associated with spi operation address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 por, bor mclr , wdt 0bh, 8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 94h sspstat smp cke d/a p s r/w ua bf 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the ssp in spi mode. note 1: these bits are reserved on the 28-pin devices; always maintain these bits clear.
? 1999 microchip technology inc. preliminary ds30221a-page 61 pic16f872 9.2 mssp i 2 c operation the mssp module in i 2 c mode fully implements all master and slave functions (including general call sup- port) and provides interrupts-on-start and stop bits in hardware to determine a free bus (multi-master func- tion). the mssp module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. refer to application note an578, "use of the ssp module in the i 2 c multi-master environment." a "glitch" filter is on the scl and sda pins when the pin is an input. this filter operates in both the 100 khz and 400 khz modes. in the 100 khz mode, when these pins are an output, there is a slew rate control of the pin that is independent of device frequency. figure 9-5: i 2 c slave mode block diagram two pins are used for data transfer. these are the scl pin, which is the clock, and the sda pin, which is the data. the sda and scl pins are automatically config- ured when the i 2 c mode is enabled. the ssp module functions are enabled by setting ssp enable bit sspen (sspcon<5>). the mssp module has six registers for i 2 c operation. they are the: ? ssp control register (sspcon) ? ssp control register2 (sspcon2) ? ssp status register (sspstat) ? serial receive/transmit buffer (sspbuf) ? ssp shift register (sspsr) - not directly accessible ? ssp address register (sspadd) the sspcon register allows control of the i 2 c opera- tion. four mode selection bits (sspcon<3:0>) allow one of the following i 2 c modes to be selected: ?i 2 c slave mode (7-bit address) ?i 2 c slave mode (10-bit address) ?i 2 c master mode, clock = osc/4 (sspadd +1) before selecting any i 2 c mode, the scl and sda pins must be programmed to inputs by setting the appropri- ate tris bits. selecting an i 2 c mode, by setting the sspen bit, enables the scl and sda pins to be used as the clock and data lines in i 2 c mode. the cke bit (sspstat<6:7>) sets the levels of the sda and scl pins in either master or slave mode. when cke = 1, the levels will conform to the smbus specification. when cke = 0, the levels will conform to the i 2 c specification. read write sspsr reg match detect sspadd reg start and stop bit detect sspbuf reg internal data bus addr match set, reset s, p bits (sspstat reg) scl shift clock msb lsb sda
pic16f872 ds30221a-page 62 preliminary ? 1999 microchip technology inc. the sspstat register gives the status of the data transfer. this information includes detection of a start (s) or stop (p) bit, specifies if the received byte was data or address, if the next byte is the comple- tion of 10-bit address, and if this will be a read or write data transfer. sspbuf is the register to which the transfer data is written to or read from. the sspsr register shifts the data in or out of the device. in receive operations, the sspbuf and sspsr create a doubled buffered receiver. this allows reception of the next byte to begin before reading the last byte of received data. when the complete byte is received, it is transferred to the sspbuf register and flag bit sspif is set. if another complete byte is received before the sspbuf register is read, a receiver overflow has occurred and bit sspov (sspcon<6>) is set and the byte in the sspsr is lost. the sspadd register holds the slave address. in 10-bit mode, the user needs to write the high byte of the address ( 1111 0 a9 a8 0 ). following the high byte address match, the low byte of the address needs to be loaded (a7:a0). 9.2.1 slave mode in slave mode, the scl and sda pins must be config- ured as inputs. the mssp module will override the input state with the output data when required (slave- transmitter). when an address is matched or the data transfer after an address match is received, the hardware automati- cally will generate the acknowledge (ack ) pulse, and then load the sspbuf register with the received value currently in the sspsr register. there are certain conditions that will cause the mssp module not to give this ack pulse. these are if either (or both): a) the buffer full bit bf (sspstat<0>) was set before the transfer was received. b) the overflow bit sspov (sspcon<6>) was set before the transfer was received. if the bf bit is set, the sspsr register value is not loaded into the sspbuf, but bit sspif and sspov are set. ta bl e 9 - 2 shows what happens when a data trans- fer byte is received, given the status of bits bf and sspov. the shaded cells show the condition where user software did not properly clear the overflow condi- tion. flag bit bf is cleared by reading the sspbuf reg- ister, while bit sspov is cleared through software. the scl clock input must have a minimum high and low time for proper operation. the high and low times of the i 2 c specification, as well as the requirement of the mssp module, is shown in timing parameter #100 and parameter #101 of the electrical specifications. 9.2.1.1 addressing once the mssp module has been enabled, it waits for a start condition to occur. following the start con- dition, the 8-bits are shifted into the sspsr register. all incoming bits are sampled with the rising edge of the clock (scl) line. the value of register sspsr<7:1> is compared to the value of the sspadd register. the address is compared on the falling edge of the eighth clock (scl) pulse. if the addresses match, and the bf and sspov bits are clear, the following events occur: a) the sspsr register value is loaded into the sspbuf register on the falling edge of the 8th scl pulse. b) the buffer full bit, bf, is set on the falling edge of the 8th scl pulse. c) an ack pulse is generated. d) ssp interrupt flag bit, sspif (pir1<3>), is set (interrupt is generated if enabled) on the falling edge of the 9th scl pulse. in 10-bit address mode, two address bytes need to be received by the slave. the five most significant bits (msbs) of the first address byte specify if this is a 10-bit address. bit r/w (sspstat<2>) must specify a write so the slave device will receive the second address byte. for a 10-bit address, the first byte would equal 1111 0 a9 a8 0 , where a9 and a8 are the two msbs of the address. the sequence of events for a 10-bit address is as follows, with steps 7- 9 for slave- transmitter: 1. receive first (high) byte of address (bits sspif, bf and ua (sspstat<1>) are set). 2. update the sspadd register with the second (low) byte of address (clears bit ua and releases the scl line). 3. read the sspbuf register (clears bit bf) and clear flag bit sspif. 4. receive second (low) byte of address (bits sspif, bf and ua are set). 5. update the sspadd register with the first (high) byte of address. this will clear bit ua and release the scl line. 6. read the sspbuf register (clears bit bf) and clear flag bit sspif. 7. receive repeated start condition. 8. receive first (high) byte of address (bits sspif and bf are set). 9. read the sspbuf register (clears bit bf) and clear flag bit sspif. note: following the repeated start condition (step 7) in 10-bit mode, the user only needs to match the first 7-bit address. the user does not update the sspadd for the second half of the address.
? 1999 microchip technology inc. preliminary ds30221a-page 63 pic16f872 9.2.1.2 slave reception when the r/w bit of the address byte is clear and an address match occurs, the r/w bit of the sspstat register is cleared. the received address is loaded into the sspbuf register. when the address byte overflow condition exists, then no acknowledge (ack ) pulse is given. an overflow con- dition is defined as either bit bf (sspstat<0>) is set or bit sspov (sspcon<6>) is set. an ssp interrupt is generated for each data transfer byte. flag bit sspif (pir1<3>) must be cleared in soft- ware. the sspstat register is used to determine the status of the received byte. table 9-2 data transfer received byte actions 9.2.1.3 slave transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspstat register is set. the received address is loaded into the sspbuf register. the ack pulse will be sent on the ninth bit, and the scl pin is held low. the transmit data must be loaded into the sspbuf register, which also loads the sspsr register. then the scl pin should be enabled by setting bit ckp (ssp- con<4>). the master must monitor the scl pin prior to asserting another clock pulse. the slave devices may be holding off the master by stretching the clock. the eight data bits are shifted out on the falling edge of the scl input. this ensures that the sda signal is valid during the scl high time ( figure 9-7 ). an ssp interrupt is generated for each data transfer byte. the sspif flag bit must be cleared in software and the sspstat register is used to determine the sta- tus of the byte transfer. the sspif flag bit is set on the falling edge of the ninth clock pulse. as a slave-transmitter, the ack pulse from the master receiver is latched on the rising edge of the ninth scl input pulse. if the sda line is high (not ack ), then the data transfer is complete. when the not ack is latched by the slave, the slave logic is reset and the slave then monitors for another occurrence of the start bit. if the sda line was low (ack ), the transmit data must be loaded into the sspbuf register, which also loads the sspsr register. then the scl pin should be enabled by setting the ckp bit. figure 9-6: i 2 c waveforms for reception (7-bit address) note: the sspbuf will be loaded if the sspov bit is set and the bf flag is cleared. if a read of the sspbuf was performed, but the user did not clear the state of the sspov bit before the next receive occurred, the ack is not sent and the ssp- buf is updated. status bits as data transfer is received sspsr ? sspbuf generate ack pulse set bit sspif (ssp interrupt occurs if enabled) bf sspov 00 ye s ye s ye s 10 no no yes 11 no no yes 0 1 ye s no ye s note 1: shaded cells show the conditions where the user software did not properly clear the overflow condition. p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 12 3 4 5 6 7 8 9 12 3 4 56 7 89 123 4 bus master terminates transfer bit sspov is set because the sspbuf register is still full. cleared in software sspbuf register is read ack receiving data receiving data d0 d1 d2 d3 d4 d5 d6 d7 ack r/w =0 receiving address sspif bf (sspstat<0>) sspov (sspcon<6>) ack ack is not sent. not
pic16f872 ds30221a-page 64 preliminary ? 1999 microchip technology inc. figure 9-7: i 2 c waveforms for transmission (7-bit address) 9.2.2 general call address support the addressing procedure for the i 2 c bus is such that the first byte after the start condition usually deter- mines which device will be the slave addressed by the master. the exception is the general call address, which can address all devices. when this address is used, all devices should, in theory, respond with an acknowledge. the general call address is one of eight addresses reserved for specific purposes by the i 2 c protocol. it consists of all 0s with r/w = 0 the general call address is recognized when the gen- eral call enable bit (gcen) is enabled (sspcon2<7> is set). following a start-bit detect, 8 bits are shifted into sspsr and the address is compared against sspadd. it is also compared to the general call address and fixed in hardware. if the general call address matches, the sspsr is transferred to the sspbuf, the bf flag is set (eighth bit), and on the falling edge of the ninth bit (ack bit), the sspif flag is set. when the interrupt is serviced, the source for the inter- rupt can be checked by reading the contents of the sspbuf to determine if the address was device spe- cific or a general call address. in 10-bit mode, the sspadd is required to be updated for the second half of the address to match, and the ua bit is set (sspstat<1>). if the general call address is sampled when gcen is set while the slave is config- ured in 10-bit address mode, then the second half of the address is not necessary, the ua bit will not be set, and the slave will begin receiving data after the acknowledge ( figure 9-8 ). figure 9-8: slave mode general call address sequence (7 or 10-bit mode) sda scl sspif bf (sspstat<0>) ckp (sspcon<4>) a7 a6 a5 a4 a3 a2 a1 ack d7 d6 d5 d4 d3 d2 d1 d0 not ack transmitting data r/w = 1 receiving address 123456789 123456789 p cleared in software sspbuf is written in software from ssp interrupt service routine set bit after writing to sspbuf s data in sampled scl held low while cpu responds to sspif (the sspbuf must be written-to before the ckp bit can be set) r/w = 0 sda scl s sspif bf sspov cleared in software sspbuf is read r/w = 0 ack general call address address is compared to general call address gcen receiving data ack 123456789123456789 d7 d6 d5 d4 d3 d2 d1 d0 after ack, set interrupt flag '0' '1' (sspstat<0>) (sspcon<6>) (sspcon2<7>)
? 1999 microchip technology inc. preliminary ds30221a-page 65 pic16f872 9.2.3 sleep operation while in sleep mode, the i 2 c module can receive addresses or data. when an address match or com- plete byte transfer occurs, wake the processor from sleep (if the ssp interrupt is enabled). 9.2.4 effects of a reset a reset disables the ssp module and terminates the current transfer. table 9-3 registers associated with i 2 c operation address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 por, bor mclr , wdt 0bh, 8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 (1) adif (1) (1) sspif ccp1if tmr2if tmr1if r0rr 0000 r0rr 0000 8ch pie1 (1) adie (1) (1) sspie ccp1ie tmr2ie tmr1ie r0rr 0000 r0rr 0000 0dh pir2 (1) eeif bclif (1) -r-0 0--r -r-0 0--r 8dh pie2 (1) eeie bclie (1) -r-0 0--r -r-0 0--r 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 91h sspcon2 gcen ackstat ackdt acken rcen pen rsen sen 0000 0000 0000 0000 94h sspstat smp cke d/a psr/w ua bf 0000 0000 0000 0000 legend: x = unknown, u = unchanged, r= reserved, - = unimplemented read as '0'. shaded cells are not used by the ssp in i 2 c mode. note 1: these bits are reserved; always maintain these bits clear.
pic16f872 ds30221a-page 66 preliminary ? 1999 microchip technology inc. 9.2.5 master mode master mode of operation is supported by interrupt generation on the detection of the start and stop conditions. the stop (p) and start (s) bits are cleared from a reset or when the mssp module is disabled. control of the i 2 c bus may be tacken when the p bit is set, or the bus is idle with both the s and p bits clear. in master mode, the scl and sda lines are manipu- lated by the mssp hardware. the following events will cause the ssp interrupt flag bit, sspif, to be set (ssp interrupt if enabled): ? start condition ? stop condition ? data transfer byte transmitted/received ? acknowledge transmit ? repeated start figure 9-9: ssp block diagram (i 2 c master mode) read write sspsr start bit, stop bit, start bit detect, sspbuf internal data bus set/reset, s, p, wcol (sspstat) shift clock msb lsb sda acknowledge generate stop bit detect write collision detect clock arbitration state counter for end of xmit/rcv scl scl in bus collision sda in receive enable clock cntl clock arbitrate/wcol detect (hold off clock source) sspadd<6:0> baud set sspif, bclif reset ackstat, pen (sspcon2) rate generator sspm<3:0>,
? 1999 microchip technology inc. preliminary ds30221a-page 67 pic16f872 9.2.6 multi-master mode in multi-master mode, the interrupt generation on the detection of the start and stop conditions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset or when the mssp module is disabled. control of the i 2 c bus may be tacken when bit p (sspstat<4>) is set, or the bus is idle with both the s and p bits clear. when the bus is busy, enabling the ssp interrupt will gener- ate the interrupt when the stop condition occurs. in multi-master operation, the sda line must be moni- tored for arbitration to see if the signal level is the expected output level. this check is performed in hard- ware, with the result placed in the bclif bit. the states where arbitration can be lost are: ? address transfer ? data transfer ? a start condition ? a repeated start condition ? an acknowledge condition 9.2.7 i 2 c master mode support master mode is enabled by setting and clearing the appropriate sspm bits in sspcon and by setting the sspen bit. once master mode is enabled, the user has six options. - assert a start condition on sda and scl. - assert a repeated start condition on sda and scl. - write to the sspbuf register initiating trans- mission of data/address. - generate a stop condition on sda and scl. - configure the i 2 c port to receive data. - generate an acknowledge condition at the end of a received byte of data. 9.2.7.4 i 2 c master mode operation the master device generates all of the serial clock pulses and the start and stop conditions. a trans- fer is ended with a stop condition or with a repeated start condition. since the repeated start condition is also the beginning of the next serial transfer, the i 2 c bus will not be released. in master transmitter mode, serial data is output through sda, while scl outputs the serial clock. the first byte transmitted contains the slave address of the receiving device (7 bits) and the read/write (r/w ) bit. in this case, the r/w bit will be logic '0'. serial data is transmitted 8 bits at a time. after each byte is transmit- ted, an acknowledge bit is received. start and stop conditions are output to indicate the beginning and the end of a serial transfer. in master receive mode, the first byte transmitted con- tains the slave address of the transmitting device (7 bits) and the r/w bit. in this case, the r/w bit will be logic '1'. thus, the first byte transmitted is a 7-bit slave address followed by a '1' to indicate receive bit. serial data is received via sda, while scl outputs the serial clock. serial data is received 8 bits at a time. after each byte is received, an acknowledge bit is transmitted. start and stop conditions indicate the beginning and end of transmission. the baud rate generator used for spi mode operation is now used to set the scl clock frequency for either 100 khz, 400 khz or 1 mhz i 2 c operation. the baud rate generator reload value is contained in the lower 7 bits of the sspadd register. the baud rate generator will automatically begin counting on a write to the sspbuf. once the given operation is complete (i.e., transmission of the last data bit is followed by ack), the internal clock will automatically stop counting and the scl pin will remain in its last state a typical transmit sequence would go as follows: a) the user generates a start condition by setting the start enable bit (sen) in sspcon2. b) sspif is set. the module will wait the required start time before any other operation takes place. c) the user loads the sspbuf with address to transmit. d) address is shifted out the sda pin until all 8 bits are transmitted. e) the mssp module shifts in the ack bit from the slave device and writes its value into the sspcon2 register ( sspcon2<6>). f) the module generates an interrupt at the end of the ninth clock cycle by setting sspif. g) the user loads the sspbuf with eight bits of data. h) data is shifted out the sda pin until all 8 bits are transmitted. note: the mssp module, when configured in i 2 c master mode, does not allow queueing of events. for instance, the user is not allowed to initiate a start condition and immediately write the sspbuf register to initiate transmission before the start condition is complete. in this case, the sspbuf will not be written to and the wcol bit will be set, indicating that a write to the sspbuf did not occur.
pic16f872 ds30221a-page 68 preliminary ? 1999 microchip technology inc. i) the mssp module shifts in the ack bit from the slave device, and writes its value into the sspcon2 register ( sspcon2<6>). j) the mssp module generates an interrupt at the end of the ninth clock cycle by setting the sspif bit. k) the user generates a stop condition by setting the stop enable bit pen in sspcon2. l) interrupt is generated once the stop condition is complete. 9.2.8 baud rate generator in i 2 c master mode, the reload value for the brg is located in the lower 7 bits of the sspadd register ( figure 9-10 ). when the brg is loaded with this value, the brg counts down to 0 and stops until another reload has tacken place. the brg count is decre- mented twice per instruction cycle (t cy ), on the q2 and q4 clock. in i 2 c master mode, the brg is reloaded automatically. if clock arbitration is taking place for instance, the brg will be reloaded when the scl pin is sampled high ( figure 9-11 ). figure 9-10: baud rate generator block diagram figure 9-11: baud rate generator timing with clock arbitration sspm<3:0> brg down counter clkout f osc /4 sspadd<6:0> sspm<3:0> scl reload control reload sda scl scl deasserted but slave holds dx-1 dx brg scl is sampled high, reload takes place, and brg starts its count. 03h 02h 01h 00h (hold off) 03h 02h reload brg value scl low (clock arbitration) scl allowed to transition high brg decrements (on q2 and q4 cycles)
? 1999 microchip technology inc. preliminary ds30221a-page 69 pic16f872 9.2.9 i 2 c master mode start condition timing to initiate a start condition, the user sets the start condition enable bit, sen (sspcon2<0>). if the sda and scl pins are sampled high, the baud rate genera- tor is re-loaded with the contents of sspadd<6:0> and starts its count. if scl and sda are both sampled high when the baud rate generator times out (t brg ), the sda pin is driven low. the action of the sda being driven low while scl is high is the start condition, and causes the s bit (sspstat<3>) to be set. follow- ing this, the baud rate generator is reloaded with the contents of sspadd<6:0> and resumes its count. when the baud rate generator times out (t brg ), the sen bit (sspcon2<0>) will be automatically cleared by hardware. the baud rate generator is suspended leaving the sda line held low, and the start condition is complete. 9.2.9.5 wcol status flag if the user writes the sspbuf when an start sequence is in progress, then wcol is set and the contents of the buffer are unchanged (the write doesnt occur). figure 9-12: first start bit timing note: if at the beginning of start condition the sda and scl pins are already sampled low, or if during the start condition the scl line is sampled low before the sda line is driven low, a bus collision occurs, the bus collision interrupt flag (bclif) is set, the start condition is aborted, and the i 2 c module is reset into its idle state. note: because queueing of events is not allowed, writing to the lower 5 bits of sspcon2 is disabled until the start condition is complete. sda scl s t brg 1st bit 2nd bit t brg sda = 1, at completion of start bit, scl = 1 write to sspbuf occurs here t brg hardware clears sen bit t brg write to sen bit occurs here. set s bit (sspstat<3>) and sets sspif bit
pic16f872 ds30221a-page 70 preliminary ? 1999 microchip technology inc. 9.2.10 i 2 c master mode repeated start condition timing a repeated start condition occurs when the rsen bit (sspcon2<1>) is programmed high and the i 2 c mod- ule is in the idle state. when the rsen bit is set, the scl pin is asserted low. when the scl pin is sampled low, the baud rate generator is loaded with the contents of sspadd<6:0> and begins counting. the sda pin is released (brought high) for one baud rate generator count (t brg ). when the baud rate generator times out if sda is sampled high, the scl pin will be deasserted (brought high). when scl is sampled high the baud rate generator is reloaded with the contents of sspadd<6:0> and begins counting. sda and scl must be sampled high for one t brg . this action is then followed by assertion of the sda pin (sda is low) for one t brg , while scl is high. following this, the rsen bit in the sspcon2 register will be automatically cleared and the baud rate generator will not be reloaded, leaving the sda pin held low. as soon as a start condition is detected on the sda and scl pins, the s bit (sspstat<3>) will be set. the sspif bit will not be set until the baud rate generator has timed-out. immediately following the sspif bit getting set, the user may write the sspbuf with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. after the first eight bits are transmitted and an ack is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode). 9.2.10.6 wcol status flag if the user writes the sspbuf when a repeated start sequence is in progress, then wcol is set and the contents of the buffer are unchanged (the write doesnt occur). figure 9-13: repeat start condition waveform note 1: if rsen is programmed while any other event is in progress, it will not take effect. note 2: a bus collision during the repeated start condition occurs if: ? sda is sampled low when scl goes from low to high. ? scl goes low before sda is asserted low. this may indicate that another master is attempting to transmit a data "1". note: because queueing of events is not allowed, writing of the lower 5 bits of sspcon2 is disabled until the repeated start condition is complete. sda scl sr = repeated start write to sspcon2 write to sspbuf occurs here. falling edge of ninth clock end of xmit at completion of start bit, hardware clear rsen bit 1st bit set s (sspstat<3>) t brg t brg sda = 1, sda = 1, scl(no change) scl = 1 occurs here. t brg t brg t brg and set sspif
? 1999 microchip technology inc. preliminary ds30221a-page 71 pic16f872 9.2.11 i 2 c master mode transmission transmission of a data byte, a 7-bit address or either half of a 10-bit address, is accomplished by simply writ- ing a value to sspbuf register. this action will set the buffer full flag (bf) and allow the baud rate generator to begin counting and start the next transmission. each bit of address/data will be shifted out onto the sda pin after the falling edge of scl is asserted (see data hold time spec). scl is held low for one baud rate gener- ator rollover count (t brg ). data should be valid before scl is released high (see data setup time spec). when the scl pin is released high, it is held that way for t brg . the data on the sda pin must remain stable for that duration and some hold time after the next fall- ing edge of scl. after the eighth bit is shifted out (the falling edge of the eighth clock), the bf flag is cleared and the master releases sda allowing the slave device being addressed to respond with an ack bit during the ninth bit time, if an address match occurs or if data was received properly. the status of ack is read into the ackdt on the falling edge of the ninth clock. if the master receives an acknowledge, the acknowledge status bit (ackstat) is cleared. if not, the bit is set. after the ninth clock, the sspif is set and the master clock (baud rate generator) is suspended until the next data byte is loaded into the sspbuf, leaving scl low and sda unchanged ( figure 9-14 ). after the write to the sspbuf, each bit of address will be shifted out on the falling edge of scl until all seven address bits and the r/w bit are completed. on the fall- ing edge of the eighth clock, the master will de-assert the sda pin allowing the slave to respond with an acknowledge. on the falling edge of the ninth clock, the master will sample the sda pin to see if the address was recognized by a slave. the status of the ack bit is loaded into the ackstat status bit (sspcon2<6>). following the falling edge of the ninth clock transmis- sion of the address, the sspif is set, the bf flag is cleared, and the baud rate generator is turned off until another write to the sspbuf takes place, holding scl low and allowing sda to float. 9.2.11.7 bf status flag in transmit mode, the bf bit (sspstat<0>) is set when the cpu writes to sspbuf and is cleared when all 8 bits are shifted out. 9.2.11.8 wcol status flag if the user writes the sspbuf when a transmit is already in progress (i.e., sspsr is still shifting out a data byte), then wcol is set and the contents of the buffer are unchanged (the write doesnt occur). wcol must be cleared in software. 9.2.11.9 ackstat status flag in transmit mode, the ackstat bit (sspcon2<6>) is cleared when the slave has sent an acknowledge (ack = 0) and is set when the slave does not acknowl- edge (ack = 1). a slave sends an acknowledge when it has recognized its address (including a general call) or when the slave has properly received its data.
pic16f872 ds30221a-page 72 preliminary ? 1999 microchip technology inc. figure 9-14: i 2 c master mode timing (transmission, 7 or 10-bit address) sda scl sspif bf (sspstat<0>) sen a7 a6 a5 a4 a3 a2 a1 ack = 0 d7d6d5d4d3d2d1d0 ack transmitting data or second half r/w = 0 transmit address to slave 123456789 123456789 p cleared in software service routine sspbuf is written in software from ssp interrupt after start condition sen cleared by hardware. s sspbuf written with 7-bit address and r/w start transmit scl held low while cpu responds to sspif sen = 0 of 10-bit address write sspcon2<0> sen = 1 start condition begins from slave clear ackstat bit sspcon2<6> ackstat in sspcon2 = 1 cleared in software sspbuf written pen cleared in software r/w
? 1999 microchip technology inc. preliminary ds30221a-page 73 pic16f872 9.2.12 i 2 c master mode reception master mode reception is enabled by programming the receive enable bit, rcen (sspcon2<3>). the baud rate generator begins counting, and on each rollover, the state of the scl pin changes (high to low/low to high), and data is shifted into the sspsr. after the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the sspsr are loaded into the sspbuf, the bf flag is set, the sspif is set, and the baud rate generator is sus- pended from counting, holding scl low. the ssp is now in idle state, awaiting the next command. when the buffer is read by the cpu, the bf flag is automati- cally cleared. the user can then send an acknowledge bit at the end of reception, by setting the acknowledge sequence enable bit, acken (sspcon2<4>). 9.2.12.10 bf status flag in receive operation, bf is set when an address or data byte is loaded into sspbuf from sspsr. it is cleared when sspbuf is read. 9.2.12.11 sspov status flag in receive operation, sspov is set when 8 bits are received into the sspsr and the bf flag is already set from a previous reception. 9.2.12.12 wcol status flag if the user writes the sspbuf when a receive is already in progress (i.e., sspsr is still shifting in a data byte), then wcol is set and the contents of the buffer are unchanged (the write doesnt occur). note: the ssp module must be in an idle state before the rcen bit is set or the rcen bit will be disregarded.
pic16f872 ds30221a-page 74 preliminary ? 1999 microchip technology inc. figure 9-15: i 2 c master mode timing (reception 7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 12 3 4 5 6 7 8 9 12 3 4 5 678 9 1234 bus master terminates transfer ack receiving data from slave receiving data from slave d0 d1 d2 d3 d4 d5 d6 d7 ack r/w = 1 transmit address to slave sspif bf ack is not sent write to sspcon2<0> (sen = 1) write to sspbuf occurs here ack from slave master configured as a receiver by programming sspcon2<3>, (rcen = 1) pen bit = 1 written here data shifted in on falling edge of clk cleared in software start xmit sen = 0 sspov sda = 0, scl = 1 while cpu (sspstat<0>) ack last bit is shifted into sspsr and contents are unloaded into sspbuf cleared in software cleared in software set sspif interrupt at end of receive set p bit (sspstat<4>) and sspif cleared in software ack from master set sspif at end set sspif interrupt at end of acknowledge sequence set sspif interrupt at end of acknow- ledge sequence of receive set acken start acknowledge sequence sspov is set because sspbuf is still full sda = ackdt = 1 rcen cleared automatically rcen = 1 start next receive write to sspcon2<4> to start acknowledge sequence sda = ackdt (sspcon2<5>) = 0 rcen cleared automatically responds to sspif acken begin start condition cleared in software sda = ackdt = 0
? 1999 microchip technology inc. preliminary ds30221a-page 75 pic16f872 9.2.13 acknowledge sequence timing an acknowledge sequence is enabled by setting the acknowledge sequence enable bit, acken (sspcon2<4>). when this bit is set, the scl pin is pulled low and the contents of the acknowledge data bit is presented on the sda pin. if the user wishes to generate an acknowledge, the ackdt bit should be cleared. if not, the user should set the ackdt bit before starting an acknowledge sequence. the baud rate generator then counts for one rollover period (t brg ), and the scl pin is deasserted (pulled high). when the scl pin is sampled high (clock arbitration), the baud rate generator counts for t brg . the scl pin is then pulled low. following this, the acken bit is auto- matically cleared, the baud rate generator is turned off, and the ssp module then goes into idle mode. ( figure 9-16 ) 9.2.13.13 wcol status flag if the user writes the sspbuf when an acknowledege sequence is in progress, the wcol is set and the con- tents of the buffer are unchanged (the write doesnt occur). figure 9-16: acknowledge sequence waveform note: t brg = one baud rate generator period. sda scl set sspif at the end acknowledge sequence starts here, write to sspcon2 acken automatically cleared cleared in t brg t brg of receive ack 8 acken = 1, ackdt = 0 d0 9 sspif software set sspif at the end of acknowledge sequence cleared in software
pic16f872 ds30221a-page 76 preliminary ? 1999 microchip technology inc. 9.2.14 stop condition timing a stop bit is asserted on the sda pin at the end of a receive/transmit by setting the stop sequence enable bit pen (sspcon2<2>). at the end of a receive/trans- mit, the scl line is held low after the falling edge of the ninth clock. when the pen bit is set, the master will assert the sda line low . when the sda line is sam- pled low, the baud rate generator is reloaded and counts down to 0. when the baud rate generator times out, the scl pin will be brought high, and one t brg (baud rate generator rollover count) later, the sda pin will be deasserted. when the sda pin is sampled high while scl is high, the p bit (sspstat<4>) is set. a t brg later, the pen bit is cleared and the sspif bit is set ( figure 9-17 ). whenever the firmware decides to take control of the bus, it will first determine if the bus is busy by checking the s and p bits in the sspstat register. if the bus is busy, then the cpu can be interrupted (notified) when a stop bit is detected (i.e., bus is free). 9.2.14.14 wcol status flag if the user writes the sspbuf when a stop sequence is in progress, then wcol is set and the contents of the buffer are unchanged (the write doesnt occur). figure 9-17: stop condition receive or transmit mode scl sda sda asserted low before rising edge of clock write to sspcon2 set pen falling edge of scl = 1 for t brg , followed by sda = 1 for t brg 9th clock scl brought high after t brg note: t brg = one baud rate generator period. t brg t brg after sda sampled high. p bit (sspstat<4>) is set t brg to setup stop condition. ack p t brg pen bit (sspcon2<2>) is cleared by hardware and the sspif bit is set
? 1999 microchip technology inc. preliminary ds30221a-page 77 pic16f872 9.2.15 clock arbitration clock arbitration occurs when the master, during any receive, transmit, or repeated start/stop condition, deasserts the scl pin (scl allowed to float high). when the scl pin is allowed to float high, the baud rate generator (brg) is suspended from counting until the scl pin is actually sampled high. when the scl pin is sampled high, the baud rate generator is reloaded with the contents of sspadd<6:0> and begins counting. this ensures that the scl high time will always be at least one brg rollover count in the event that the clock is held low by an external device ( figure 9-18 ). 9.2.16 sleep operation while in sleep mode, the i 2 c module can receive addresses or data, and when an address match or complete byte transfer occurs, wake the processor from sleep (if the ssp interrupt is enabled). 9.2.17 effects of a reset a reset disables the ssp module and terminates the current transfer. figure 9-18: clock arbitration timing in master transmit mode scl sda brg overflow, release scl, if scl = 1 load brg with sspadd<6:0>, and start count brg overflow occurs, release scl, slave device holds scl low. scl = 1 brg starts counting clock high interval. scl line sampled once every machine cycle (t osc 4). hold off brg until scl is sampled high. t brg t brg t brg to measure high time interval
pic16f872 ds30221a-page 78 preliminary ? 1999 microchip technology inc. 9.2.18 multi -master communication, bus collision, and bus arbitration multi-master mode support is achieved by bus arbitra- tion. when the master outputs address/data bits onto the sda pin, arbitration takes place when the master outputs a '1' on sda by letting sda float high and another master asserts a '0'. when the scl pin floats high, data should be stable. if the expected data on sda is a '1' and the data sampled on the sda pin = '0', a bus collision has taken place. the master will set the bus collision interrupt flag, bclif, and reset the i 2 c port to its idle state. ( figure 9-19 ). if a transmit was in progress when the bus collision occurred, the transmission is halted, the bf flag is cleared, the sda and scl lines are deasserted, and the sspbuf can be written to. when the user services the bus collision interrupt service routine, and if the i 2 c bus is free, the user can resume communication by asserting a start condition. if a start, repeated start, stop or acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the sda and scl lines are deasserted, and the respective control bits in the sspcon2 register are cleared. when the user services the bus collision interrupt service routine, and if the i 2 c bus is free, the user can resume communica- tion by asserting a start condition. the master will continue to monitor the sda and scl pins, and if a stop condition occurs, the sspif bit will be set. a write to the sspbuf will start the transmission of data at the first data bit, regardless of where the trans- mitter left off when the bus collision occurred. in multi-master mode, the interrupt generation on the detection of start and stop conditions allows the deter- mination of when the bus is free. control of the i 2 c bus can be taken when the p bit is set in the sspstat reg- ister, or the bus is idle and the s and p bits are cleared. figure 9-19: bus collision timing for transmit and acknowledge sda scl bclif sda released sda line pulled low by another source sample sda. while scl is high, data doesnt match what is driven bus collision has occurred. set bus collision interrupt. by the master. by master data changes while scl = 0
? 1999 microchip technology inc. preliminary ds30221a-page 79 pic16f872 9.2.18.15 bus collision during a start condition during a start condition, a bus collision occurs if: a) sda or scl are sampled low at the beginning of the start condition ( figure 9-20 ). b) scl is sampled low before sda is asserted low. ( figure 9-21 ). during a start condition both the sda and the scl pins are monitored. if: the sda pin is already low or the scl pin is already low, then: the start condition is aborted, and the bclif flag is set, and the ssp module is reset to its idle state ( figure 9-20 ). the start condition begins with the sda and scl pins deasserted. when the sda pin is sampled high, the baud rate generator is loaded from sspadd<6:0> and counts down to 0. if the scl pin is sampled low while sda is high, a bus collision occurs, because it is assumed that another master is attempting to drive a data '1' during the start condition. if the sda pin is sampled low during this count, the brg is reset and the sda line is asserted early ( figure 9-22 ). if, however, a '1' is sampled on the sda pin, the sda pin is asserted low at the end of the brg count. the baud rate generator is then reloaded and counts down to 0. during this time, if the scl pins are sampled as '0', a bus collision does not occur. at the end of the brg count, the scl pin is asserted low. figure 9-20: bus collision during start condition (sda only) note: the reason that bus collision is not a factor during a start condition is that no two bus masters can assert a start condition at the exact same time. therefore, one master will always assert sda before the other. this condition does not cause a bus collision, because the two masters must be allowed to arbitrate the first address follow- ing the start condition. if the address is the same, arbitration must be allowed to continue into the data portion, repeated start or stop conditions. sda scl sen sda sampled low before sda goes low before the sen bit is set. s bit and sspif set because ssp module reset into idle state. sen cleared automatically because of bus collision. s bit and sspif set because set sen, enable start condition if sda = 1, scl=1 sda = 0, scl = 1 bclif s sspif sda = 0, scl = 1 sspif and bclif are cleared in software. sspif and bclif are cleared in software. set bclif, set bclif. start condition.
pic16f872 ds30221a-page 80 preliminary ? 1999 microchip technology inc. figure 9-21: bus collision during start condition (scl = 0) figure 9-22: brg reset due to sda collision during start condition sda scl sen bus collision occurs, set bclif scl = 0 before sda = 0, set sen, enable start sequence if sda = 1, scl = 1 t brg t brg sda = 0, scl = 1 bclif s sspif interrupts cleared in software bus collision occurs, set bclif scl = 0 before brg time out, '0' '0' '0' '0' sda scl sen set s set sen, enable start sequence if sda = 1, scl = 1 less than t brg t brg sda = 0, scl = 1 bclif s sspif s interrupts cleared in software set sspif sda = 0, scl = 1 sda pulled low by other master reset brg and assert sda scl pulled low after brg timeout set sspif '0'
? 1999 microchip technology inc. preliminary ds30221a-page 81 pic16f872 9.2.18.16 bus collision during a repeated start condition during a repeated start condition, a bus collision occurs if: a) a low level is sampled on sda when scl goes from low level to high level. b) scl goes low before sda is asserted low, indi- cating that another master is attempting to trans- mit a data 1. when the user deasserts sda and the pin is allowed to float high, the brg is loaded with sspadd<6:0> and counts down to 0. the scl pin is then deasserted, and when sampled high, the sda pin is sampled. if sda is low, a bus collision has occurred (i.e., another master is attempting to transmit a data 0). if, however, sda is sampled high, the brg is reloaded and begins count- ing. if sda goes from high to low before the brg times out, no bus collision occurs, because no two masters can assert sda at exactly the same time. if, however, scl goes from high to low before the brg times out and sda has not already been asserted, a bus collision occurs. in this case, another master is attempting to transmit a data 1 during the repeated start condition. if, at the end of the brg time out, both scl and sda are still high, the sda pin is driven low, the brg is reloaded and begins counting. at the end of the count, regardless of the status of the scl pin, the scl pin is driven low and the repeated start condition is com- plete ( figure 9-23 ). figure 9-23: bus collision during a repeated start condition (case 1) figure 9-24: bus collision during repeated start condition (case 2) sda scl rsen bclif s sspif sample sda when scl goes high. if sda = 0, set bclif and release sda and scl cleared in software '0' '0' '0' '0' sda scl bclif rsen s sspif interrupt cleared in software scl goes low before sda, set bclif. release sda and scl t brg t brg '0' '0' '0' '0'
pic16f872 ds30221a-page 82 preliminary ? 1999 microchip technology inc. 9.2.18.17 bus collision during a stop condition bus collision occurs during a stop condition if: a) after the sda pin has been deasserted and allowed to float high, sda is sampled low after the brg has timed out. b) after the scl pin is deasserted, scl is sampled low before sda goes high. the stop condition begins with sda asserted low. when sda is sampled low, the scl pin is allow to float. when the pin is sampled high (clock arbitration), the baud rate generator is loaded with sspadd<6:0> and counts down to 0. after the brg times out, sda is sampled. if sda is sampled low, a bus collision has occurred. this is due to another master attempting to drive a data '0'. if the scl pin is sampled low before sda is allowed to float high, a bus collision occurs. this is a case of another master attempting to drive a data '0' ( figure 9-25 ). figure 9-25: bus collision during a stop condition (case 1) figure 9-26: bus collision during a stop condition (case 2) sda scl bclif pen p sspif t brg t brg t brg sda asserted low sda sampled low after t brg , set bclif. '0' '0' '0' '0' sda scl bclif pen p sspif t brg t brg t brg assert sda scl goes low before sda goes high set bclif '0' '0'
? 1999 microchip technology inc. preliminary ds30221a-page 83 pic16f872 9.3 connection considerations for i 2 c bus for standard-mode i 2 c bus devices, the values of resistors r p and r s in figure 9-27 depend on the fol- lowing parameters: ? supply voltage ? bus capacitance ? number of connected devices (input current + leakage current). the supply voltage limits the minimum value of resistor r p due to the specified minimum sink current of 3 ma at v ol max = 0.4v for the specified output stages. for example, with a supply voltage of v dd = 5v+ 10% and v ol max = 0.4v at 3 ma, r p min = (5.5-0.4)/0.003 = 1.7 k w. v dd as a function of r p is shown in figure 9-27. the desired noise margin of 0.1v dd for the low level limits the maximum value of r s . series resistors are optional and used to improve esd susceptibility. the bus capacitance is the total capacitance of wire, connections, and pins. this capacitance limits the max- imum value of r p due to the specified rise time ( figure 9-27 ). the smp bit is the slew rate control enabled bit. this bit is in the sspstat register, and controls the slew rate of the i/o pins when in i 2 c mode (master or slave). figure 9-27: sample device configuration for i 2 c bus rp rp v dd + 10% sda scl device c b =10 - 400 pf rs rs note: i 2 c devices with input levels related to v dd must have one common supply line to which the pull-up resistor is also connected.
pic16f872 ds30221a-page 84 preliminary ? 1999 microchip technology inc. notes:
? 1999 microchip technology inc. preliminary ds30221a-page 85 pic16f872 10.0 analog-to-digital converter (a/d) module the analog-to-digital (a/d) converter module has five inputs. the analog input charges a sample and hold capacitor. the output of the sample and hold capacitor is the input into the converter. the converter then generates a digital result of this analog level via successive approximation. the a/d conversion of the analog input signal results in a corresponding 10-bit digital number. the a/d module has high and low voltage reference input that is software selectable to some combination of v dd , v ss , ra2 or ra3. the a/d converter has a unique feature of being able to operate while the device is in sleep mode. to operate in sleep, the a/d clock must be derived from the a/ds internal rc oscillator. the a/d module has four registers. these registers are: ? a/d result high register (adresh) ? a/d result low register (adresl) ? a/d control register0 (adcon0) ? a/d control register1 (adcon1) the adcon0 register, shown in register 10-1, con- trols the operation of the a/d module. the adcon1 register, shown in register 10-2, configures the func- tions of the port pins. the port pins can be configured as analog inputs (ra3 can also be the voltage refer- ence) or as digital i/o. additional information on using the a/d module can be found in the picmicro? mid-range mcu family ref- erence manual (ds33023). register 10-1: adcon0 register (address: 1fh) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 adcs1 adcs0 chs2 chs1 chs0 go/done adon r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7-6: adcs<1:0>: a/d conversion clock select bits 00 = f osc /2 01 = f osc /8 10 = f osc /32 11 = f rc (clock derived from an rc oscillation) bit 5-3: chs<2:0> : analog channel select bits 000 = channel 0, (ra0/an0) 001 = channel 1, (ra1/an1) 010 = channel 2, (ra2/an2) 011 = channel 3, (ra3/an3) 100 = channel 4, (ra5/an4) bit 2: go/done : a/d conversion status bit if adon = 1 1 = a/d conversion in progress (setting this bit starts the a/d conversion) 0 = a/d conversion not in progress (this bit is automatically cleared by hardware when the a/d conversion is complete) bit 1: unimplemented : read as '0' bit 0: adon : a/d on bit 1 = a/d converter module is operating 0 = a/d converter module is shutoff and consumes no operating current
pic16f872 ds30221a-page 86 preliminary ? 1999 microchip technology inc. register 10-2: adcon1 register (address 9fh) u-0 u-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 adfm pcfg3 pcfg2 pcfg1 pcfg0 r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7: adfm: a/d result format select 1 = right justified. 6 most significant bits of adresh are read as 0. 0 = left justified. 6 least significant bits of adresl are read as 0. bit 6-4: unimplemented: read as '0' bit 3-0: pcfg<3:0> : a/d port configuration control bits a = analog input d = digital i/o note 1: this column indicates the number of analog channels available as a/d inputs and the number of analog channels used as voltage reference inputs. pcfg<3:0> an4 ra5 an3 ra3 an2 ra2 an1 ra1 an0 ra0 v ref +v ref - c han / refs (1) 0000 a a aaav dd v ss 5/0 0001 av ref +aaara3v ss 4/1 0010 a a aaav dd v ss 5/0 0011 av ref +aaara3v ss 4/1 0100 dadaav dd v ss 3/0 0101 dv ref +d a a ra3 v ss 2/1 011x d d dddv dd v ss 0/0 1000 av ref +v ref -a a ra3ra2 3/2 1001 a a aaav dd v ss 5/0 1010 av ref +aaara3v ss 4/1 1011 av ref +v ref -a a ra3ra2 3/2 1100 av ref +v ref -a a ra3ra2 3/2 1101 dv ref +v ref -a a ra3ra2 2/2 1110 ddddav dd v ss 1/0 1111 dv ref +v ref -d a ra3ra2 1/2
? 1999 microchip technology inc. preliminary ds30221a-page 87 pic16f872 the adresh:adresl registers contain the 10-bit result of the a/d conversion. when the a/d conversion is complete, the result is loaded into this a/d result reg- ister pair, the go/done bit (adcon0<2>) is cleared and the a/d interrupt flag bit adif is set. the block dia- gram of the a/d module is shown in figure 10-1. after the a/d module has been configured as desired, the selected channel must be acquired before the con- version is started. the analog input channels must have their corresponding tris bits selected as inputs. to determine sample time, see section 10.1. after this acquisition time has elapsed, the a/d conversion can be started. the following steps should be followed for doing an a/d conversion: 1. configure the a/d module: ? configure analog pins / voltage reference / and digital i/o (adcon1) ? select a/d input channel (adcon0) ? select a/d conversion clock (adcon0) ? turn on a/d module (adcon0) 2. configure a/d interrupt (if desired): ? clear adif bit ? set adie bit ? set gie bit 3. wait the required acquisition time. 4. start conversion: ? set go/done bit (adcon0) 5. wait for a/d conversion to complete, by either: ? polling for the go/done bit to be cleared or ? waiting for the a/d interrupt 6. read a/d result register pair (adresh:adresl), clear bit adif if required. 7. for next conversion, go to step 1 or step 2 as required. the a/d conversion time per bit is defined as t ad . a minimum wait of 2t ad is required before next acquisition starts.
pic16f872 ds30221a-page 88 preliminary ? 1999 microchip technology inc. figure 10-1: a/d block diagram 10.1 a /d acquisition requirements for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 10-2. the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ), figure 10-2. the maximum recommended impedance for analog sources is 10 k w . as the impedance is decreased, the acquisition time may be decreased. after the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. to calculate the minimum acquisition time, equation 10-1 may be used. this equation assumes that 1/2 lsb error is used (1024 steps for the a/d). the 1/2 lsb error is the maximum error allowed for the a/d to meet its specified resolution. to calculate the minimum acquisition time, t acq , see the picmicro? mid-range reference manual (ds33023). (input voltage) v ain v ref + (reference voltage) v dd pcfg<3:0> chs<2:0> ra5/an4 ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0 100 011 010 001 000 a/d converter v ref - (reference voltage) v ss pcfg<3:0>
? 1999 microchip technology inc. preliminary ds30221a-page 89 pic16f872 equation 10-1: acquisition time figure 10-2: analog input model t acq t c t acq = = = = = = = = amplifier settling time + hold capacitor charging time + temperature coefficient t amp + t c + t coff 2 m s + t c + [(temperature -25c)(0.05 m s/c)] c hold (r ic + r ss + r s ) in(1/2047) - 120pf (1k w + 7k w + 10k w ) in(0.0004885) 16.47 m s 2 m s + 16.47 m s + [(50c -25c)(0.05 m s/c) 19.72 m s note 1: the reference voltage (v ref ) has no effect on the equation, since it cancels itself out. 2: the charge holding capacitor (c hold ) is not discharged after each conversion. 3: the maximum recommended impedance for analog sources is 10 k w . this is required to meet the pin leak- age specification. 4: after a conversion has completed, a 2.0t ad delay must complete before acquisition can begin again. during this time, the holding capacitor is not connected to the selected a/d input channel. c pin va r s anx 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss r ss c hold = dac capacitance v ss 6v sampling switch 5v 4v 3v 2v 5 6 7 8 9 10 11 ( k w ) v dd = 120 pf 500 na legend c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions
pic16f872 ds30221a-page 90 preliminary ? 1999 microchip technology inc. 10.2 selecting the a/d conversion clock the a/d conversion time per bit is defined as t ad . the a/d conversion requires a minimum 12t ad per 10-bit conversion. the source of the a/d conversion clock is software selected. the four possible options for t ad are: ?2t osc ?8t osc ?32t osc ? internal rc oscillator for correct a/d conversions, the a/d conversion clock (t ad ) must be selected to ensure a minimum t ad time of 1.6 m s. table 10-1shows the resultant t ad times derived from the device operating frequencies and the a/d clock source selected. table 10-1: t ad vs. maximum device operating frequencies (standard devices (c)) 10.3 configuring analog port pins the adcon1, and tris registers control the operation of the a/d port pins. the port pins that are desired as analog inputs must have their corresponding tris bits set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs<2:0> bits and the tris bits. ad clock source (t ad ) maximum device frequency operation adcs<1:0> max. 2t osc 00 1.25 mhz 8t osc 01 5 mhz 32t osc 10 20 mhz rc (1, 2, 3) 11 note 1 note 1: the rc source has a typical t ad time of 4 m s but can vary between 2-6 m s. 2: when the device frequencies are greater than 1 mhz, the rc a/d conversion clock source is only recommended for sleep operation. 3: for extended voltage devices (lc), please refer to the electrical specifications section. note 1: when reading the port register, any pin configured as an analog input channel will read as cleared (a low level). pins config- ured as digital inputs will convert an ana- log input. analog levels on a digitally configured input will not affect the conver- sion accuracy. 2: analog levels on any pin that is defined as a digital input (including the an<4:0> pins), may cause the input buffer to con- sume current that is out of the device specifications.
? 1999 microchip technology inc. preliminary ds30221a-page 91 pic16f872 10.4 a/d conversions clearing the go/done bit during a conversion will abort the current conversion. the a/d result register pair will not be updated with the partially completed a/d conversion sample. that is, the adresh:adresl registers will continue to contain the value of the last completed conversion (or the last value written to the adresh:adresl registers). after the a/d conversion is aborted, a 2t ad wait is required before the next acquisition is started. after this 2t ad wait, acquisition on the selected channel is automatically started. in figure 10-3, after the go bit is set, the first time seg- ment has a minimum of t cy and a maximum of t ad . figure 10-3: a/d conversion t ad cycles note: the go/done bit should not be set in the same instruction that turns on the a/d. t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 9 set go bit holding capacitor is disconnected from analog input (typically 100 ns) b9 b8 b7 b6 b5 b4 b3 b2 t ad 10 t ad 11 b1 b0 t cy to t ad conversion starts adres is loaded, go bit is cleared, adif bit is set, holding capacitor is connected to analog input.
pic16f872 ds30221a-page 92 preliminary ? 1999 microchip technology inc. 10.4.1 a/d result registers the adresh:adresl register pair is the location where the 10-bit a/d result is loaded at the completion of the a/d conversion. this register pair is 16-bits wide. the a/d module gives the flexibility to left or right justify the 10-bit result in the 16-bit result register. the a/d format select bit (adfm) controls this justifica- tion. figure 10-4 shows the operation of the a/d result justification. the extra bits are loaded with 0s. when an a/d result will not overwrite these locations (a/d disable), these registers may be used as two general purpose 8-bit registers. 10.5 a/d operation during sleep the a/d module can operate during sleep mode. this requires that the a/d clock source be set to rc (adcs<1:0> = 11 ). when the rc clock source is selected, the a/d module waits one instruction cycle before starting the conversion. this allows the sleep instruction to be executed, which eliminates all digital switching noise from the conversion. when the conver- sion is completed, the go/done bit will be cleared and the result loaded into the adres register. if the a/d interrupt is enabled, the device will wake-up from sleep. if the a/d interrupt is not enabled, the a/d mod- ule will then be turned off, although the adon bit will remain set. when the a/d clock source is another clock option (not rc), a sleep instruction will cause the present conver- sion to be aborted and the a/d module to be turned off, though the adon bit will remain set. turning off the a/d places the a/d module in its lowest current consumption state. 10.6 effects of a reset a device reset forces all registers to their reset state. this forces the a/d module to be turned off, and any conversion is aborted. the value that is in the adresh:adresl registers is not modified for a power-on reset. the adresh:adresl registers will contain unknown data after a power-on reset. figure 10-4: a/d result justification note: for the a/d module to operate in sleep, the a/d clock source must be set to rc (adcs<1:0> = 11 ). to allow the conver- sion to occur during sleep, ensure the sleep instruction immediately follows the instruction that sets the go/done bit. 10-bit result adresh adresl 0000 00 adfm = 0 0 2 1 0 7 7 10-bit result adresh adresl 10-bit result 0000 00 7 0 7 6 5 0 adfm = 1 right justified left justified
? 1999 microchip technology inc. preliminary ds30221a-page 93 pic16f872 table 10-2: registers/bits associated with a/d addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 por, bor mclr , wdt 0bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 (1) adif (1) (1) sspif ccp1if tmr2if tmr1if r0rr 0000 r0rr 0000 8ch pie1 (1) adie (1) (1) sspie ccp1ie tmr2ie tmr1ie r0rr 0000 r0rr 0000 1eh adresh a/d result register high byte xxxx xxxx uuuu uuuu 9eh adresl a/d result register low byte xxxx xxxx uuuu uuuu 1fh adcon0 adcs1 adcs0 chs2 chs1 chs0 go/done adon 0000 00-0 0000 00-0 9fh adcon1 adfm pcfg3 pcfg2 pcfg1 pcfg0 --0- 0000 --0- 0000 85h trisa porta data direction register --11 1111 --11 1111 05h porta porta data latch when written: porta pins when read --0x 0000 --0u 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used for a/d conversion. note 1: these bits are reserved; always maintain these bits clear.
pic16f872 ds30221a-page 94 preliminary ? 1999 microchip technology inc. notes:
? 1999 microchip technology inc. preliminary ds30221a-page 95 pic16f872 11.0 special features of the cpu these devices have a host of features intended to max- imize system reliability, minimize cost through elimina- tion of external components, provide power saving operating modes and offer code protection. these are: ? osc selection ? reset - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - brown-out reset (bor) ? interrupts ? watchdog timer (wdt) ? sleep ? code protection ? id locations ? in-circuit serial programming ? low voltage in-circuit serial programming ? in-circuit debugger these devices have a watchdog timer, which can be shut off only through configuration bits. it runs off its own rc oscillator for added reliability. there are two timers that offer necessary delays on power-up. one is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. the other is the power-up timer (pwrt), which pro- vides a fixed delay of 72 ms (nominal) on power-up only. it is designed to keep the part in reset while the power supply stabilizes. with these two timers on-chip, most applications need no external reset circuitry. sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through external reset, watchdog timer wake-up, or through an interrupt. several oscillator options are also made available to allow the part to fit the application. the rc oscillator option saves system cost while the lp crystal option saves power. a set of configuration bits are used to select various options. additional information on special features is available in the picmicro? mid-range reference manual, (ds33023). 11.1 configuration bits the configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. these bits are mapped in pro- gram memory location 2007h. the user will note that address 2007h is beyond the user program memory space. in fact, it belongs to the special test/configuration memory space (2000h through 3fffh), which can be accessed only during programming.
pic16f872 ds30221a-page 96 preliminary ? 1999 microchip technology inc. register 11-1: configuration word cp1 cp0 debug wrt cpd lvp boden cp1 cp0 pwrte wdte f0sc1 f0sc0 register: config address 2007h bit13 bit0 bit 13-12: bit 5-4: cp<1:0>: flash program memory code protection bits (2) 11 = code protection off 10 = 0000h to 06ffh code protected 01 = 0000h to 03ffh code protected 00 = 0000h to 07ffh code protected bit 11: debug: in-circuit debugger mode 1 = in-circuit debugger disabled, rb6 and rb7 are general purpose i/o pins. 0 = in-circuit debugger enabled, rb6 and rb7 are dedicated to the debugger. bit 10: unimplemented: read as 1 bit 9: wrt: flash program memory write enable 1 = unprotected program memory may be written to by eecon control 0 = unprotected program memory may not be written to by eecon control bit 8: cpd: data ee memory code protection 1 = code protection off 0 = data eeprom memory code protected bit 7: lv p : low voltage in-circuit serial programming enable bit 1 = rb3/pgm pin has pgm function, low voltage programming enabled 0 = rb3 is digital i/o, hv on mclr must be used for programming bit 6: boden : brown-out reset enable bit (1) 1 = bor enabled 0 = bor disabled bit 3: pwrte : power-up timer enable bit (1) 1 = pwrt disabled 0 = pwrt enabled bit 2: wdte : watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1-0: fosc1:fosc0 : oscillator selection bits 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator note 1: enabling brown-out reset automatically enables power-up timer (pwrt), regardless of the value of bit pwrte . ensure the power-up timer is enabled anytime brown-out reset is enabled. 2: all of the cp<1:0> pairs have to be given the same value to enable the code protection scheme listed.
? 1999 microchip technology inc. preliminary ds30221a-page 97 pic16f872 11.2 oscillator configurations 11.2.1 oscillator types the pic16f872 can be operated in four different oscil- lator modes. the user can program two configuration bits (fosc1 and fosc0) to select one of these four modes: ? lp low power crystal ? xt crystal/resonator ? hs high speed crystal/resonator ? rc resistor/capacitor 11.2.2 crystal oscillator/ceramic resonators in xt, lp or hs modes, a crystal or ceramic resonator is connected to the osc1/clkin and osc2/clkout pins to establish oscillation (figure 11-1). the pic16f872 oscillator design requires the use of a par- allel cut crystal. use of a series cut crystal may give a frequency out of the crystal manufacturers specifica- tions. when in xt, lp or hs modes, the device can have an external clock source to drive the osc1/ clkin pin (figure 11-2). figure 11-1: crystal/ceramic resonator operation (hs, xt or lp osc configuration) figure 11-2: external clock input operation (hs, xt or lp osc configuration) table 11-1: ceramic resonators note 1: see table 11-1 and table 11-2 for rec- ommended values of c1 and c2. 2: a series resistor (rs) may be required for at strip cut crystals. 3: rf varies with the crystal chosen. c1 (1) c2 (1) xtal osc2 osc1 rf (3) sleep to logic pic16f872 rs (2) internal osc1 osc2 open clock from ext. system pic16f872 ranges tested: mode freq osc1 osc2 xt 455 khz 2.0 mhz 4.0 mhz 68 - 100 pf 15 - 68 pf 15 - 68 pf 68 - 100 pf 15 - 68 pf 15 - 68 pf hs 8.0 mhz 16.0 mhz 10 - 68 pf 10 - 22 pf 10 - 68 pf 10 - 22 pf these values are for design guidance only. see notes at bottom of page. resonators used: 455 khz panasonic efo-a455k04b 0.3% 2.0 mhz murata erie csa2.00mg 0.5% 4.0 mhz murata erie csa4.00mg 0.5% 8.0 mhz murata erie csa8.00mt 0.5% 16.0 mhz murata erie csa16.00mx 0.5% all resonators used did not have built-in capacitors.
pic16f872 ds30221a-page 98 preliminary ? 1999 microchip technology inc. table 11-2: capacitor selection for crystal oscillator 11.2.3 rc oscillator for timing insensitive applications, the rc device option offers additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resis- tor (r ext ) and capacitor (c ext ) values, and the operat- ing temperature. in addition to this, the oscillator frequency will vary from unit to unit due to normal pro- cess parameter variation. furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low c ext values. the user also needs to take into account variation due to tolerance of external r and c compo- nents used. figure 11-3 shows how the r/c combina- tion is connected to the pic16f872. figure 11-3: rc oscillator mode osc type crystal freq cap. range c1 cap. range c2 lp 32 khz 33 pf 33 pf 200 khz 15 pf 15 pf xt 200 khz 47-68 pf 47-68 pf 1 mhz 15 pf 15 pf 4 mhz 15 pf 15 pf hs 4 mhz 15 pf 15 pf 8 mhz 15-33 pf 15-33 pf 20 mhz 15-33 pf 15-33 pf these values are for design guidance only. see notes at bottom of page. crystals used 32 khz epson c-001r32.768k-a 20 ppm 200 khz std xtl 200.000khz 20 ppm 1 mhz ecs ecs-10-13-1 50 ppm 4 mhz ecs ecs-40-20-1 50 ppm 8 mhz epson ca-301 8.000m-c 30 ppm 20 mhz epson ca-301 20.000m-c 30 ppm note 1: higher capacitance increases the stability of oscillator but also increases the start-up time. 2: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external compo- nents. 3: rs may be required in hs mode, as well as xt mode, to avoid overdriving crystals with low drive level specification. 4: when migrating from other picmicro devices, oscillator performance should be verified. osc2/clkout c ext r ext pic16f872 osc1 f osc /4 internal clock v dd v ss recommended values: 3 k w r ext 100 k w c ext > 20pf
? 1999 microchip technology inc. preliminary ds30221a-page 99 pic16f872 11.3 reset the pic16f872 differentiates between various kinds of reset: ? power-on reset (por) ?mclr reset during normal operation ?mclr reset during sleep ? wdt reset (during normal operation) ? wdt wake-up (during sleep) ? brown-out reset (bor) some registers are not affected in any reset condi- tion. their status is unknown on por and unchanged in any other reset. most other registers are reset to a reset state on power-on reset (por), on the mclr and wdt reset, on mclr reset during sleep, and brown-out reset (bor). they are not affected by a wdt wake-up, which is viewed as the resumption of normal operation. the to and pd bits are set or cleared differently in different reset situations as indi- cated in table 11-4. these bits are used in software to determine the nature of the reset. see table 11-6 for a full description of reset states of all registers. a simplified block diagram of the on-chip reset circuit is shown in figure 11-4. these devices have a mclr noise filter in the mclr reset path. the filter will detect and ignore small pulses. it should be noted that a wdt reset does not drive mclr pin low. figure 11-4: simplified block diagram of on-chip reset circuit s r q external reset mclr v dd osc1 wdt module v dd rise detect ost/pwrt on-chip rc osc wdt time-out power-on reset ost 10-bit ripple counter pwrt chip_reset 10-bit ripple counter reset enable ost enable pwrt sleep note 1: this is a separate oscillator from the rc oscillator of the clkin pin. brown-out reset boden (1)
pic16f872 ds30221a-page 100 preliminary ? 1999 microchip technology inc. 11.4 power-on reset (por) a power-on reset pulse is generated on-chip when v dd rise is detected (in the range of 1.2v - 1.7v). to take advantage of the por, tie the mclr pin directly (or through a resistor) to v dd . this will eliminate exter- nal rc components usually needed to create a power- on reset. a maximum rise time for v dd is specified. see electrical specifications for details. when the device starts normal operation (exits the reset condition), device operating parameters (volt- age, frequency, temperature,...) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. brown-out reset may be used to meet the start-up conditions. for additional information, refer to application note, an007, power-up trouble shooting, (ds00007). 11.5 p ower-up timer (pwrt) the power-up timer provides a fixed 72 ms nominal time-out on power-up only from the por. the power- up timer operates on an internal rc oscillator. the chip is kept in reset as long as the pwrt is active. the pwrts time delay allows v dd to rise to an accept- able level. a configuration bit is provided to enable/dis- able the pwrt. the power-up time delay will vary from chip to chip due to v dd , temperature and process variation. see dc parameters for details (t pwrt , parameter #33). 11.6 o scillator start-up timer (ost) the oscillator start-up timer (ost) provides 1024 oscillator cycle (from osc1 input) delay after the pwrt delay is over. this ensures that the crystal oscil- lator or resonator has started and stabilized. the ost time-out is invoked only for xt, lp and hs modes and only on power-on reset or wake-up from sleep. 11.7 brown-out reset (bor) the configuration bit, boden, can enable or disable the brown-out reset circuit. if v dd falls below v bor (parameter d005, about 4v) for longer than t bor (parameter #35, about 100 m s), the brown-out situa- tion will reset the device. if v dd falls below v bor for less than t bor , a reset may not occur. once the brown-out occurs, the device will remain in brown-out reset until v dd rises above v bor . the power-up timer then keeps the device in reset for t pwrt (parameter #33, about 72ms). if v dd should fall below v bor during t pwrt , the brown-out reset process will restart when v dd rises above v bor with the power-up timer reset. the power-up timer is always enabled when the brown-out reset circuit is enabled regardless of the state of the pwrt configu- ration bit. 11.8 time-out sequence on power-up, the time-out sequence is as follows: the pwrt delay starts (if enabled) when a por reset occurs. then ost starts counting 1024 oscillator cycles when pwrt ends (lp, xt, hs). when the ost ends, the device comes out of reset. if mclr is kept low long enough, the time-outs will expire. bringing mclr high will begin execution imme- diately. this is useful for testing purposes or to synchro- nize more than one pic16cxx device operating in parallel. table 11-5 shows the reset conditions for the status, pcon and pc registers, while table 11-6 shows the reset conditions for all the registers. 11.9 p ower control/status register (pcon) the power control/status register, pcon, has up to two bits depending upon the device. bit0 is brown-out reset status bit, bor . bit bor is unknown on a power-on reset. it must then be set by the user and checked on subsequent resets to see if bit bor cleared, indicating a bor occurred. the bor bit is a "dont care" bit and is not necessarily predictable if the brown-out reset circuitry is disabled (by clearing bit boden in the configuration word). bit1 is por (power-on reset status bit). it is cleared on a power-on reset and unaffected otherwise. the user must set this bit following a power-on reset.
? 1999 microchip technology inc. preliminary ds30221a-page 101 pic16f872 table 11-3: time-out in various situations table 11-4: status bits and their significance table 11-5: reset condition for special registers oscillator configuration power-up brown-out wake-up from sleep pwrte = 0 pwrte = 1 xt, hs, lp 72 ms + 1024t osc 1024t osc 72 ms + 1024t osc 1024t osc rc 72 ms 72 ms por bor to pd 0x11 power-on reset 0x0x illegal, to is set on por 0xx0 illegal, pd is set on por 1011 brown-out reset 1101 wdt reset 1100 wdt wake-up 11uu mclr reset during normal operation 1110 mclr reset during sleep or interrupt wake-up from sleep condition program counter status register pcon register power-on reset 000h 0001 1xxx ---- --0x mclr reset during normal operation 000h 000u uuuu ---- --uu mclr reset during sleep 000h 0001 0uuu ---- --uu wdt reset 000h 0000 1uuu ---- --uu wdt wake-up pc + 1 uuu0 0uuu ---- --uu brown-out reset 000h 0001 1uuu ---- --u0 interrupt wake-up from sleep pc + 1 (1) uuu1 0uuu ---- --uu legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'. note 1: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h).
pic16f872 ds30221a-page 102 preliminary ? 1999 microchip technology inc. table 11-6: initialization conditions for all registers register power-on reset, brown-out reset mclr resets wdt reset wake-up via wdt or interrupt w xxxx xxxx uuuu uuuu uuuu uuuu indf n/a n/a n/a tmr0 xxxx xxxx uuuu uuuu uuuu uuuu pcl 0000h 0000h pc + 1 (2) status 0001 1xxx 000q quuu (3) uuuq quuu (3) fsr xxxx xxxx uuuu uuuu uuuu uuuu porta --0x 0000 --0u 0000 --uu uuuu portb xxxx xxxx uuuu uuuu uuuu uuuu portc xxxx xxxx uuuu uuuu uuuu uuuu pclath ---0 0000 ---0 0000 ---u uuuu intcon 0000 000x 0000 000u uuuu uuuu (1) pir1 r0rr 0000 r0rr 0000 rurr uuuu (1) pir2 -r-0 0--r -r-0 0--r -r-u u--r (1) tmr1l xxxx xxxx uuuu uuuu uuuu uuuu tmr1h xxxx xxxx uuuu uuuu uuuu uuuu t1con --00 0000 --uu uuuu --uu uuuu tmr2 0000 0000 0000 0000 uuuu uuuu t2con -000 0000 -000 0000 -uuu uuuu sspbuf xxxx xxxx uuuu uuuu uuuu uuuu sspcon 0000 0000 0000 0000 uuuu uuuu ccpr1l xxxx xxxx uuuu uuuu uuuu uuuu ccpr1h xxxx xxxx uuuu uuuu uuuu uuuu ccp1con --00 0000 --00 0000 --uu uuuu adresh xxxx xxxx uuuu uuuu uuuu uuuu adcon0 0000 00-0 0000 00-0 uuuu uu-u option_reg 1111 1111 1111 1111 uuuu uuuu trisa --11 1111 --11 1111 --uu uuuu trisb 1111 1111 1111 1111 uuuu uuuu trisc 1111 1111 1111 1111 uuuu uuuu pie1 r0rr 0000 r0rr 0000 rurr uuuu pie2 -r-0 0--r -r-0 0--r -r-u u--r pcon ---- --qq ---- --uu ---- --uu pr2 1111 1111 1111 1111 1111 1111 sspadd 0000 0000 0000 0000 uuuu uuuu sspstat --00 0000 --00 0000 --uu uuuu adresl xxxx xxxx uuuu uuuu uuuu uuuu adcon1 0--- 0000 0--- 0000 u--- uuuu eedata 0--- 0000 0--- 0000 u--- uuuu eeadr xxxx xxxx uuuu uuuu uuuu uuuu eedath xxxx xxxx uuuu uuuu uuuu uuuu eeadrh xxxx xxxx uuuu uuuu uuuu uuuu eecon1 x--- x000 u--- u000 u--- uuuu eecon2 ---- ---- ---- ---- ---- ---- legend: u = unchanged, x = unknown, r = reserved, - = unimplemented bit, read as '0', q = value depends on condition, r = reserved maintain clear. note 1: one or more bits in intcon, pir1 and/or pir2 will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 3: see table 11-5 for reset value for specific condition.
? 1999 microchip technology inc. preliminary ds30221a-page 103 pic16f872 figure 11-5: time-out sequence on power-up (mclr tied to v dd ) figure 11-6: time-out sequence on power-up (mclr not tied to v dd ): case 1 figure 11-7: time-out sequence on power-up (mclr not tied to v dd ): case 2 t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost
pic16f872 ds30221a-page 104 preliminary ? 1999 microchip technology inc. figure 11-8: slow rise time (mclr tied to v dd ) v dd mclr internal por pwrt time-out ost time-out internal reset 0v 1v 5v t pwrt t ost
? 1999 microchip technology inc. preliminary ds30221a-page 105 pic16f872 11.10 in terrupts the pic16f872 has 10 sources of interrupt. the inter- rupt control register (intcon) records individual inter- rupt requests in flag bits. it also has individual and global interrupt enable bits. a global interrupt enable bit, gie (intcon<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. when bit gie is enabled, and an interrupts flag bit and mask bit are set, the interrupt will vector immediately. individual interrupts can be dis- abled through their corresponding enable bits in vari- ous registers. individual interrupt bits are set regardless of the status of the gie bit. the gie bit is cleared on reset. the return from interrupt instruction, retfie , exits the interrupt routine, as well as sets the gie bit, which re-enables interrupts. the rb0/int pin interrupt, the rb port change interrupt and the tmr0 overflow interrupt flags are contained in the intcon register. the peripheral interrupt flags are contained in the spe- cial function registers, pir1 and pir2. the corre- sponding interrupt enable bits are contained in special function registers, pie1 and pie2, and the peripheral interrupt enable bit is contained in special function register intcon. when an interrupt is responded to, the gie bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the pc is loaded with 0004h. once in the interrupt service routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. the interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. for external interrupt events, such as the int pin or portb change interrupt, the interrupt latency will be three or four instruction cycles. the exact latency depends when the interrupt event occurs. the latency is the same for one or two cycle instructions. individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the gie bit figure 11-9: interrupt logic note: individual interrupt flag bits are set, regard- less of the status of their corresponding mask bit or the gie bit. sspif sspie ccp1if ccp1ie tmr2if tmr2ie tmr1if tmr1ie t0if t0ie intf inte rbif rbie gie peie wake-up (if in sleep mode) interrupt to cpu bclie bclif eeif eeie adif adie
pic16f872 ds30221a-page 106 preliminary ? 1999 microchip technology inc. 11.10.1 int interrupt external interrupt on the rb0/int pin is edge triggered, either rising, if bit intedg (option_reg<6>) is set, or falling, if the intedg bit is clear. when a valid edge appears on the rb0/int pin, flag bit intf (intcon<1>) is set. this interrupt can be disabled by clearing enable bit inte (intcon<4>). flag bit intf must be cleared in software in the interrupt service rou- tine before re-enabling this interrupt. the int interrupt can wake-up the processor from sleep, if bit inte was set prior to going into sleep. the status of global inter- rupt enable bit gie decides whether or not the proces- sor branches to the interrupt vector following wake-up. see section 11.13 for details on sleep mode. 11.10.2 tmr0 interrupt an overflow (ffh ? 00h) in the tmr0 register will set flag bit t0if (intcon<2>). the interrupt can be enabled/disabled by setting/clearing enable bit t0ie (intcon<5>) (section 5.0). 11.10.3 portb intcon change an input change on portb<7:4> sets flag bit rbif (intcon<0>). the interrupt can be enabled/disabled by setting/clearing enable bit rbie (intcon<4>) (section 3.2). 11.11 context saving during interrupts during an interrupt, only the return pc value is saved on the stack. typically, users may wish to save key reg- isters during an interrupt (i.e., w register and status register). this will have to be implemented in software. since the upper 16 bytes of each bank are common in the pic16f872 devices, temporary holding registers w_temp, status_temp and pclath_temp should be placed in here. these 16 locations dont require banking and therefore, make it easier for con- text save and restore. example 11-1 can be used to save and restore context for interrupts. example 11-1: saving status, w, and pclath registers in ram movwf w_temp ;copy w to temp register swapf status,w ;swap status to be saved into w clrf status ;bank 0, regardless of current bank, clears irp,rp1,rp0 movwf status_temp ;save status to bank zero status_temp register movf pclath, w ;only required if using pages 1, 2 and/or 3 movwf pclath_temp ;save pclath into w clrf pclath ;page zero, regardless of current page : :(isr) : movf pclath_temp, w ;restore pclath movwf pclath ;move w into pclath swapf status_temp,w ;swap status_temp register into w ;(sets bank to original state) movwf status ;move w into status register swapf w_temp,f ;swap w_temp swapf w_temp,w ;swap w_temp into w
? 1999 microchip technology inc. preliminary ds30221a-page 107 pic16f872 11.12 watchdog timer (wdt) the watchdog timer is as a free running on-chip rc oscillator which does not require any external compo- nents. this rc oscillator is separate from the rc oscil- lator of the osc1/clkin pin. that means that the wdt will run, even if the clock on the osc1/clkin and osc2/clkout pins of the device has been stopped, for example, by execution of a sleep instruction. during normal operation, a wdt time-out generates a device reset (watchdog timer reset). if the device is in sleep mode, a wdt time-out causes the device to wake-up and continue with normal operation (watch- dog timer wake-up). the to bit in the status regis- ter will be cleared upon a watchdog timer time-out. the wdt can be permanently disabled by clearing configuration bit wdte (section 11.1). wdt time-out period values may be found in the elec- trical specifications section under parameter #31. val- ues for the wdt prescaler (actually a postscaler, but shared with the timer0 prescaler) may be assigned using the option_reg register. . figure 11-10: watchdog timer block diagram figure 11-11: summary of watchdog timer registers note: the clrwdt and sleep instructions clear the wdt and the postscaler, if assigned to the wdt, and prevent it from timing out and generating a device reset condition. note: when a clrwdt instruction is executed and the prescaler is assigned to the wdt, the prescaler count will be cleared, but the prescaler assignment is not changed. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2007h config. bits (1) boden (1) cp1 cp0 pwrte (1) wdte fosc1 fosc0 81h,181h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 legend: shaded cells are not used by the watchdog timer. note 1: see register 11-1 for operation of these bits. from tmr0 clock source ( figure 5-1 ) to t m r 0 ( figure 5-1 ) postscaler wdt timer wdt enable bit 0 1 m u x psa 8 - to - 1 mux ps<2:0> 0 1 mux psa wdt time-out note: psa and ps<2:0> are bits in the option_reg register. 8
pic16f872 ds30221a-page 108 preliminary ? 1999 microchip technology inc. 11.13 power-down mode (sleep) power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, the pd bit (status<3>) is cleared, the to (status<4>) bit is set, and the oscillator driver is turned off. the i/o ports maintain the status they had before the sleep instruction was executed (driving high, low, or hi-impedance). for lowest current consumption in this mode, place all i/o pins at either v dd or v ss , ensure no external cir- cuitry is drawing current from the i/o pin, power-down the a/d and disable external clocks. pull all i/o pins that are hi-impedance inputs, high or low externally, to avoid switching currents caused by floating inputs. the t0cki input should also be at v dd or v ss for lowest current consumption. the contribution from on-chip pull-ups on portb should be considered. the mclr pin must be at a logic high level (v ihmc ). 11.13.1 wake-up from sleep the device can wake up from sleep through one of the following events: 1. external reset input on mclr pin. 2. watchdog timer wake-up (if wdt was enabled). 3. interrupt from int pin, rb port change or some peripheral interrupts. external mclr reset will cause a device reset. all other events are considered a continuation of program execution and cause a "wake-up". the to and pd bits in the status register can be used to determine the cause of device reset. the pd bit, which is set on power-up, is cleared when sleep is invoked. the to bit is cleared if a wdt time-out occurred and caused wake-up. the following peripheral interrupts can wake the device from sleep: 1. tmr1 interrupt. timer1 must be operating as an asynchronous counter. 2. ccp capture mode interrupt. 3. special event trigger (timer1 in asynchronous mode using an external clock). 4. ssp (start/stop) bit detect interrupt. 5. ssp transmit or receive in slave mode (spi/i 2 c). 6. a/d conversion (when a/d clock source is rc). 7. eeprom write operation completion. other peripherals cannot generate interrupts since dur- ing sleep, no on-chip clocks are present. when the sleep instruction is being executed, the next instruction (pc + 1) is pre-fetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). wake-up is regardless of the state of the gie bit. if the gie bit is clear (disabled), the device continues execution at the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruction and then branches to the inter- rupt address (0004h). in cases where the execution of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. 11.13.2 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: ? if the interrupt occurs before the execution of a sleep instruction, the sleep instruction will com- plete as a nop . therefore, the wdt and wdt postscaler will not be cleared, the to bit will not be set and pd bits will not be cleared. ? if the interrupt occurs during or after the execu- tion of a sleep instruction, the device will imme- diately wake up from sleep. the sleep instruction will be completely executed before the wake-up. therefore, the wdt and wdt postscaler will be cleared, the to bit will be set and the pd bit will be cleared. even if the flag bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop . to ensure that the wdt is cleared, a clrwdt instruc- tion should be executed before a sleep instruction.
? 1999 microchip technology inc. preliminary ds30221a-page 109 pic16f872 figure 11-12: wake-up from sleep through interrupt 11.14 in-circuit debugger when the debug bit in the configuration word is pro- grammed to a '0', the in-circuit debugger functionality is enabled. this function allows simple debugging func- tions when used with mplab ? . when the microcontrol- ler has this feature enabled, some of the resources are not available for general use. table 11-7 shows which features are consumed by the background debugger. table 11-7: debugger resources to use the in-circuit debugger function of the micro- controller, the design must implement in-circuit serial programming connections to mclr /v pp , v dd , gnd, rb7 and rb6. this will interface to the in-circuit debugger module available from microchip or one of the third party development tool companies. 11.15 program verification/code protection if the code protection bit(s) have not been pro- grammed, the on-chip program memory can be read out for verification purposes. 11.16 id locations four memory locations (2000h - 2003h) are designated as id locations where the user can store checksum or other code-identification numbers. these locations are not accessible during normal execution but are read- able and writable during program/verify. it is recom- mended that only the 4 least significant bits of the id location are used. q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clkout (4) int pin intf flag (intcon<1>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed pc pc+1 pc+2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (note 2) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dummy cycle pc + 2 0004h 0005h dummy cycle t ost (2) pc+2 note 1: xt, hs or lp oscillator mode assumed. 2: t ost = 1024t osc (drawing not to scale) this delay will not be there for rc osc mode. 3: gie = '1' assumed. in this case after wake- up, the processor jumps to the interrupt routine. if gie = '0', execution will continue in-line. 4: clkout is not available in these osc modes, but shown here for timing reference. i/o pins rb6, rb7 stack 1 level program memory address 0000h must be nop last 100h words data memory 0x070(0x0f0, 0x170, 0x1f0) 0x1eb - 0x1ef
pic16f872 ds30221a-page 110 preliminary ? 1999 microchip technology inc. 11.17 in-circuit serial programming the pic16f872 microcontroller can be serially pro- grammed while in the end application circuit. this is simply done with two lines for clock and data and three other lines for power, ground, and the programming voltage. this allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. this also allows the most recent firmware or a custom firm- ware to be programmed. when using icsp, the part must be supplied 4.5v to 5.5v if a bulk erase will be executed. this includes reprogramming of the code protect both from an on- state to off-state. for all other cases of icsp, the part may be programmed at the normal operating voltages. this means calibration values, unique user ids or user code can be reprogrammed or added. for complete details of serial programming, please refer to the in-circuit serial programming (icsp?) guide, (ds30277). 11.18 low voltage icsp programming the lvp bit of the configuration word enables low volt- age icsp programming. this mode allows the micro- controller to be programmed via icsp using a v dd source in the operating voltage range. this only means that v pp does not have to be brought to v ihh , but can instead be left at the normal operating voltage. in this mode, the rb3/pgm pin is dedicated to the program- ming function and ceases to be a general purpose i/o pin. during programming, v dd is applied to the mclr pin. to enter programming mode, v dd must be applied to the rb3/pgm provided the lvp bit is set. the lvp bit defaults to on (1) from the factory. if low-voltage programming mode is not used, the lvp bit can be programmed to a '0' and rb3/pgm becomes a digital i/o pin. however, the lvp bit may only be pro- grammed when programming is entered with v ihh on mclr . the lvp bit can only be charged when using high voltage on mclr . it should be noted, that once the lvp bit is programmed to 0, only the high voltage programming mode is avail- able and only high voltage programming mode can be used to program the device. when using low voltage icsp, the part must be sup- plied 4.5v to 5.5v if a bulk erase will be executed. this includes reprogramming of the code protect bits from an on-state to off-state. for all other cases of low volt- age icsp, the part may be programmed at the normal operating voltage. this means calibration values, unique user ids or user code can be reprogrammed or added. note 1: the high voltage programming mode is always available, regardless of the state of the lvp bit, by applying v ihh to the mclr pin. 2: while in low voltage icsp mode, the rb3 pin can no longer be used as a general purpose i/o pin. 3: when using low voltage icsp program- ming (lvp) and the pull-ups on portb are enabled, bit 3 in the trisb register must be cleared to disable the pull-up on rb3 and ensure the proper operation of the device.
? 1999 microchip technology inc. preliminary ds30221a-page 111 pic16f872 12.0 instruction set summary each pic16cxx instruction is a 14-bit word divided into an opcode which specifies the instruction type and one or more operands which further specify the operation of the instruction. the pic16cxx instruction set summary in table 12-2 lists byte-oriented , bit- oriented , and literal and control operations. table 12-1 shows the opcode field descriptions. for byte-oriented instructions, 'f' represents a file reg- ister designator and 'd' represents a destination desig- nator. the file register designator specifies which file register is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if 'd' is zero, the result is placed in the w register. if 'd' is one, the result is placed in the file register specified in the instruction. for bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. for literal and control operations, 'k' represents an eight or eleven bit constant or literal value. table 12-1: opcode field descriptions the instruction set is highly orthogonal and is grouped into three basic categories: ? byte-oriented operations ? bit-oriented operations ? literal and control operations all instructions are executed within one single instruc- tion cycle, unless a conditional test is true or the pro- gram counter is changed as a result of an instruction. in this case, the execution takes two instruction cycles with the second cycle executed as a nop . one instruc- tion cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 m s. if a conditional test is true or the program counter is changed as a result of an instruc- tion, the instruction execution time is 2 m s. table 12-2 lists the instructions recognized by the mpasm assembler. figure 12-1 shows the general formats that the instruc- tions can have. all examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit. figure 12-1: general format for instructions a description of each instruction is available in the picmicro? mid-range reference manual, (ds33023). field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don't care location (= 0 or 1 ) the assembler will generate code with x = 0 . it is the recommended form of use for compati- bility with all microchip software tools. d destination select; d = 0 : store result in w, d = 1: store result in file register f. default is d = 1 pc program counter to time-out bit pd power-down bit note: to maintain upward compatibility with future pic16cxx products, do not use the option and tris instructions. byte-oriented file register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit file register address bit-oriented file register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit file register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only
pic16f872 ds30221a-page 112 preliminary ? 1999 microchip technology inc. table 12-2: pic16cxxx instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z z z z c c c,dc,z z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3 literal and control operations addlw andlw call clrwdt goto iorlw movlw retfie retlw return sleep sublw xorlw k k k - k k k - k - - k k add literal and w and literal with w call subroutine clear watchdog timer go to address inclusive or literal with w move literal to w return from interrupt return with literal in w return from subroutine go into standby mode subtract w from literal exclusive or literal with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c,dc,z z to ,pd z to ,pd c,dc,z z note 1: when an i/o register is modified as a function of itself ( e.g., movf portb, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the timer0 module. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . note: additional information on the mid-range instruction set is available in the picmicro ? mid-range mcu family reference manual (ds33023).
? 1999 microchip technology inc. preliminary ds30221a-page 113 pic16f872 12.1 instruction descriptions addlw add literal and w syntax: [ label ] addlw k operands: 0 k 255 operation: (w) + k ? (w) status affected: c, dc, z description: the contents of the w register are added to the eight bit literal 'k' and the result is placed in the w register. addwf add w and f syntax: [ label ] addwf f,d operands: 0 f 127 d ? [0,1] operation: (w) + (f) ? (destination) status affected: c, dc, z description: add the contents of the w register with register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in reg- ister 'f'. andlw and literal with w syntax: [ label ] andlw k operands: 0 k 255 operation: (w) .and. (k) ? (w) status affected: z description: the contents of w register are anded with the eight bit literal 'k'. the result is placed in the w register. andwf and w with f syntax: [ label ] andwf f,d operands: 0 f 127 d ? [0,1] operation: (w) .and. (f) ? (destination) status affected: z description: and the w register with register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in register 'f'. bcf bit clear f syntax: [ label ] bcf f,b operands: 0 f 127 0 b 7 operation: 0 ? (f) status affected: none description: bit 'b' in register 'f' is cleared. bsf bit set f syntax: [ label ] bsf f,b operands: 0 f 127 0 b 7 operation: 1 ? (f) status affected: none description: bit 'b' in register 'f' is set.
pic16f872 ds30221a-page 114 preliminary ? 1999 microchip technology inc. btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 f 127 0 b < 7 operation: skip if (f) = 1 status affected: none description: if bit 'b' in register 'f' is '0', the next instruction is executed. if bit 'b' is '1', then the next instruc- tion is discarded and a nop is exe- cuted instead making this a 2t cy instruction. btfsc bit test, skip if clear syntax: [ label ] btfsc f,b operands: 0 f 127 0 b 7 operation: skip if (f) = 0 status affected: none description: if bit 'b' in register 'f' is '1', the next instruction is executed. if bit 'b', in register 'f', is '0', the next instruction is discarded, and a nop is executed instead, making this a 2t cy instruction. call call subroutine syntax: [ label ] call k operands: 0 k 2047 operation: (pc)+ 1 ? tos, k ? pc<10:0>, (pclath<4:3>) ? pc<12:11> status affected: none description: call subroutine. first, return address (pc+1) is pushed onto the stack. the eleven bit immedi- ate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pclath. call is a two cycle instruction. clrf clear f syntax: [ label ] clrf f operands: 0 f 127 operation: 00h ? (f) 1 ? z status affected: z description: the contents of register 'f' are cleared and the z bit is set. clrw clear w syntax: [ label ] clrw operands: none operation: 00h ? (w) 1 ? z status affected: z description: w register is cleared. zero bit (z) is set. clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h ? wdt 0 ? wdt prescaler, 1 ? to 1 ? pd status affected: to , pd description: clrwdt instruction resets the watchdog timer. it also resets the prescaler of the wdt. status bits to and pd are set.
? 1999 microchip technology inc. preliminary ds30221a-page 115 pic16f872 comf complement f syntax: [ label ] comf f,d operands: 0 f 127 d ? [0,1] operation: (f ) ? (destination) status affected: z description: the contents of register 'f' are complemented. if 'd' is 0, the result is stored in w. if 'd' is 1, the result is stored back in register 'f'. decf decrement f syntax: [ label ] decf f,d operands: 0 f 127 d ? [0,1] operation: (f) - 1 ? (destination) status affected: z description: decrement register 'f'. if 'd' is 0, the result is stored in the w regis- ter. if 'd' is 1, the result is stored back in register 'f'. decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 f 127 d ? [0,1] operation: (f) - 1 ? (destination); skip if result = 0 status affected: none description: the contents of register 'f' are decremented. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in reg- ister 'f'. if the result is 1, the next instruc- tion is executed. if the result is 0, then a nop is executed instead making it a 2t cy instruction. goto unconditional branch syntax: [ label ] goto k operands: 0 k 2047 operation: k ? pc<10:0> pclath<4:3> ? pc<12:11> status affected: none description: goto is an unconditional branch. the eleven bit immediate value is loaded into pc bits <10:0>. the upper bits of pc are loaded from pclath<4:3>. goto is a two cycle instruction. incf increment f syntax: [ label ] incf f,d operands: 0 f 127 d ? [0,1] operation: (f) + 1 ? (destination) status affected: z description: the contents of register 'f' are incremented. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in reg- ister 'f'. incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 f 127 d ? [0,1] operation: (f) + 1 ? (destination), skip if result = 0 status affected: none description: the contents of register 'f' are incremented. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in regis- ter 'f'. if the result is 1, the next instruc- tion is executed. if the result is 0, a nop is executed instead making it a 2t cy instruction.
pic16f872 ds30221a-page 116 preliminary ? 1999 microchip technology inc. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 k 255 operation: (w) .or. k ? (w) status affected: z description: the contents of the w register are ored with the eight bit literal 'k'. the result is placed in the w reg- ister. iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 f 127 d ? [0,1] operation: (w) .or. (f) ? (destination) status affected: z description: inclusive or the w register with register 'f'. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in regis- ter 'f'. movf move f syntax: [ label ] movf f,d operands: 0 f 127 d ? [0,1] operation: (f) ? (destination) status affected: z description: the contents of register f are moved to a destination dependant upon the status of d. if d = 0, des- tination is w register. if d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag z is affected. movlw move literal to w syntax: [ label ] movlw k operands: 0 k 255 operation: k ? (w) status affected: none description: the eight bit literal 'k' is loaded into w register. the dont cares will assemble as 0s. movwf move w to f syntax: [ label ] movwf f operands: 0 f 127 operation: (w) ? (f) status affected: none description: move data from w register to reg- ister 'f'. nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none description: no operation.
? 1999 microchip technology inc. preliminary ds30221a-page 117 pic16f872 retfie return from interrupt syntax: [ label ] retfie operands: none operation: tos ? pc, 1 ? gie status affected: none retlw return with literal in w syntax: [ label ] retlw k operands: 0 k 255 operation: k ? (w); tos ? pc status affected: none description: the w register is loaded with the eight bit literal 'k'. the program counter is loaded from the top of the stack (the return address). this is a two cycle instruction. return return from subroutine syntax: [ label ] return operands: none operation: tos ? pc status affected: none description: return from subroutine. the stack is poped and the top of the stack (tos) is loaded into the program counter. this is a two cycle instruction. rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 f 127 d ? [0,1] operation: see description below status affected: c description: the contents of register 'f' are rotated one bit to the left through the carry flag. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is stored back in register 'f'. rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 f 127 d ? [0,1] operation: see description below status affected: c description: the contents of register 'f' are rotated one bit to the right through the carry flag. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in reg- ister 'f'. sleep syntax: [ label ] sleep operands: none operation: 00h ? wdt, 0 ? wdt prescaler, 1 ? to , 0 ? pd status affected: to , pd description: the power-down status bit, pd is cleared. time-out status bit, to is set. watchdog timer and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. register f c register f c
pic16f872 ds30221a-page 118 preliminary ? 1999 microchip technology inc. sublw subtract w from literal syntax: [ label ] sublw k operands: 0 k 255 operation: k - (w) ? ( w) status affected: c, dc, z description: the w register is subtracted (2s complement method) from the eight bit literal 'k'. the result is placed in the w register. subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 f 127 d ? [0,1] operation: (f) - (w) ? ( destination) status affected: c, dc, z description: subtract (2s complement method) w register from register 'f'. if 'd' is 0, the result is stored in the w regis- ter. if 'd' is 1, the result is stored back in register 'f'. swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 f 127 d ? [0,1] operation: (f<3:0>) ? (destination<7:4>), (f<7:4>) ? (destination<3:0>) status affected: none description: the upper and lower nibbles of register 'f' are exchanged. if 'd' is 0, the result is placed in w regis- ter. if 'd' is 1, the result is placed in register 'f'. xorlw exclusive or literal with w syntax: [ label ] xorlw k operands: 0 k 255 operation: (w) .xor. k ? ( w) status affected: z description: the contents of the w register are xored with the eight bit lit- eral 'k'. the result is placed in the w register. xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 f 127 d ? [0,1] operation: (w) .xor. (f) ? ( destination) status affected: z description: exclusive or the contents of the w register with register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in register 'f'.
? 1999 microchip technology inc. preliminary ds30221a-page 119 pic16f872 13.0 development support the picmicro ? microcontrollers are supported with a full range of hardware and software development tools: ? integrated development environment - mplab ? ide software ? assemblers/compilers/linkers - mpasm assembler - mplab-c17 and mplab-c18 c compilers - mplink/mplib linker/librarian ? simulators - mplab-sim software simulator ?emulators - mplab-ice real-time in-circuit emulator - picmaster ? /picmaster-ce in-circuit emulator - icepic? ? in-circuit debugger - mplab-icd for pic16f877 ? device programmers -pro mate a ii universal programmer - picstart a plus entry-level prototype programmer ? low-cost demonstration boards - simice - picdem-1 - picdem-2 - picdem-3 - picdem-17 - seeval a -k ee l oq a 13.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8-bit microcon- troller market. mplab is a windows a -based applica- tion which contains: ? multiple functionality -editor - simulator - programmer (sold separately) - emulator (sold separately) ? a full featured editor ? a project manager ? customizable tool bar and key mapping ? a status bar ? on-line help mplab allows you to: ? edit your source files (either assembly or c) ? one touch assemble (or compile) and download to picmicro tools (automatically updates all project information) ? debug using: - source files - absolute listing file - object code the ability to use mplab with microchips simulator, mplab-sim, allows a consistent platform and the abil- ity to easily switch from the cost-effective simulator to the full featured emulator with minimal retraining. 13.2 mpasm assembler mpasm is a full featured universal macro assembler for all picmicro mcus. it can produce absolute code directly in the form of hex files for device program- mers, or it can generate relocatable objects for mplink. mpasm has a command line interface and a windows shell and can be used as a standalone application on a windows 3.x or greater system. mpasm generates relocatable object files, intel standard hex files, map files to detail memory usage and symbol reference, an absolute lst file which contains source lines and gen- erated machine code, and a cod file for mplab debugging. mpasm features include: ? mpasm and mplink are integrated into mplab projects. ? mpasm allows user defined macros to be created for streamlined assembly. ? mpasm allows conditional assembly for multi pur- pose source files. ? mpasm directives allow complete control over the assembly process. 13.3 mplab-c17 and mplab-c18 c compilers the mplab-c17 and mplab-c18 code development systems are complete ansi c compilers and inte- grated development environments for microchips pic17cxxx and pic18cxxx family of microcontrol- lers, respectively. these compilers provide powerful integration capabilities and ease of use not found with other compilers. for easier source level debugging, the compilers pro- vide symbol information that is compatible with the mplab ide memory display.
pic16f872 ds30221a-page 120 preliminary ? 1999 microchip technology inc. 13.4 mplink/mplib linker/librarian mplink is a relocatable linker for mpasm and mplab-c17 and mplab-c18. it can link relocatable objects from assembly or c source files along with pre- compiled libraries using directives from a linker script. mplib is a librarian for pre-compiled code to be used with mplink. when a routine from a library is called from another source file, only the modules that contains that routine will be linked in with the application. this allows large libraries to be used efficiently in many dif- ferent applications. mplib manages the creation and modification of library files. mplink features include: ? mplink works with mpasm and mplab-c17 and mplab-c18. ? mplink allows all memory areas to be defined as sections to provide link-time flexibility. mplib features include: ? mplib makes linking easier because single librar- ies can be included instead of many smaller files. ? mplib helps keep code maintainable by grouping related modules together. ? mplib commands allow libraries to be created and modules to be added, listed, replaced, deleted, or extracted. 13.5 mplab-sim software simulator the mplab-sim software simulator allows code development in a pc host environment by simulating the picmicro series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file or user-defined key press to any of the pins. the execution can be performed in single step, execute until break, or trace mode. mplab-sim fully supports symbolic debugging using mplab-c17 and mplab-c18 and mpasm. the soft- ware simulator offers the flexibility to develop and debug code outside of the laboratory environment mak- ing it an excellent multi-project software development tool. 13.6 mplab-ice high performance universal in-circuit emulator with mplab ide the mplab-ice universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for picmicro microcontrollers (mcus). software control of mplab-ice is provided by the mplab integrated development environment (ide), which allows editing, make and download, and source debugging from a single environment. interchangeable processor modules allow the system to be easily reconfigured for emulation of different pro- cessors. the universal architecture of the mplab-ice allows expansion to support new picmicro microcon- trollers. the mplab-ice emulator system has been designed as a real-time emulation system with advanced fea- tures that are generally found on more expensive devel- opment tools. the pc platform and microsoft ? windows 3.x/95/98 environment were chosen to best make these features available to you, the end user. mplab-ice 2000 is a full-featured emulator system with enhanced trace, trigger, and data monitoring fea- tures. both systems use the same processor modules and will operate across the full operating speed range of the picmicro mcu. 13.7 picmaster/picmaster ce the picmaster system from microchip technology is a full-featured, professional quality emulator system. this flexible in-circuit emulator provides a high-quality, universal platform for emulating microchip 8-bit picmicro microcontrollers (mcus). picmaster sys- tems are sold worldwide, with a ce compliant model available for european union (eu) countries. 13.8 icepic icepic is a low-cost in-circuit emulation solution for the microchip technology pic16c5x, pic16c6x, pic16c7x, and pic16cxxx families of 8-bit one-time- programmable (otp) microcontrollers. the modular system can support different subsets of pic16c5x or pic16cxxx products through the use of interchangeable personality modules or daughter boards. the emulator is capable of emulating without target application circuitry being present. 13.9 mplab-icd in-circuit debugger microchip's in-circuit debugger, mplab-icd, is a pow- erful, low-cost run-time development tool. this tool is based on the flash pic16f877 and can be used to develop for this and other picmicro microcontrollers from the pic16cxxx family. mplab-icd utilizes the in-circuit debugging capability built into the pic16f87x. this feature, along with microchip's in-cir- cuit serial programming protocol, offers cost-effective in-circuit flash programming and debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by watching variables, single-stepping and setting break points. running at full speed enables testing hardware in real-time. the mplab-icd is also a programmer for the flash pic16f87x family.
? 1999 microchip technology inc. preliminary ds30221a-page 121 pic16f872 13.10 pro mate ii universal programmer the pro mate ii universal programmer is a full-fea- tured programmer capable of operating in stand-alone mode as well as pc-hosted mode. pro mate ii is ce compliant. the pro mate ii has programmable v dd and v pp supplies which allows it to verify programmed memory at v dd min and v dd max for maximum reliability. it has an lcd display for instructions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. in stand-alone mode the pro mate ii can read, verify or program picmicro devices. it can also set code-protect bits in this mode. 13.11 picstart plus entry level development system the picstart programmer is an easy-to-use, low- cost prototype programmer. it connects to the pc via one of the com (rs-232) ports. mplab integrated development environment software makes using the programmer simple and efficient. picstart plus supports all picmicro devices with up to 40 pins. larger pin count devices such as the pic16c92x, and pic17c76x may be supported with an adapter socket. picstart plus is ce compliant. 13.12 simice entry-level hardware simulator simice is an entry-level hardware development sys- tem designed to operate in a pc-based environment with microchips simulator mplab-sim. both simice and mplab-sim run under microchip technologys mplab integrated development environment (ide) software. specifically, simice provides hardware sim- ulation for microchips pic12c5xx, pic12ce5xx, and pic16c5x families of picmicro 8-bit microcontrollers. simice works in conjunction with mplab-sim to pro- vide non-real-time i/o port emulation. simice enables a developer to run simulator code for driving the target system. in addition, the target system can provide input to the simulator code. this capability allows for simple and interactive debugging without having to manually generate mplab-sim stimulus files. simice is a valu- able debugging tool for entry-level system develop- ment. 13.13 picdem-1 low-cost picmicro demonstration board the picdem-1 is a simple board which demonstrates the capabilities of several of microchips microcontrol- lers. the microcontrollers supported are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the users can program the sample microcontrollers provided with the picdem-1 board, on a pro mate ii or picstart-plus programmer, and easily test firm- ware. the user can also connect the picdem-1 board to the mplab-ice emulator and download the firmware to the emulator for testing. additional proto- type area is available for the user to build some addi- tional hardware and connect it to the microcontroller socket(s). some of the features include an rs-232 interface, a potentiometer for simulated analog input, push-button switches and eight leds connected to portb. 13.14 picdem-2 low-cost pic16cxx demonstration board the picdem-2 is a simple demonstration board that supports the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcontrollers. all the necessary hardware and software is included to run the basic demonstration programs. the user can program the sample microcontrollers provided with the picdem-2 board, on a pro mate ii pro- grammer or picstart-plus, and easily test firmware. the mplab-ice emulator may also be used with the picdem-2 board to test firmware. additional prototype area has been provided to the user for adding addi- tional hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 inter- face, push-button switches, a potentiometer for simu- lated analog input, a serial eeprom to demonstrate usage of the i 2 c bus and separate headers for connec- tion to an lcd module and a keypad. 13.15 picdem-3 low-cost pic16cxxx demonstration board the picdem-3 is a simple demonstration board that supports the pic16c923 and pic16c924 in the plcc package. it will also support future 44-pin plcc microcontrollers with a lcd module. all the neces- sary hardware and software is included to run the basic demonstration programs. the user can pro- gram the sample microcontrollers provided with the picdem-3 board, on a pro mate ii program- mer or picstart plus with an adapter socket, and easily test firmware. the mplab-ice emulator may also be used with the picdem-3 board to test firm- ware. additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). some of the features include an rs-232 interface, push-button switches, a potenti- ometer for simulated analog input, a thermistor and separate headers for connection to an external lcd module and a keypad. also provided on the picdem-3 board is an lcd panel, with 4 commons and 12 seg- ments, that is capable of displaying time, temperature and day of the week. the picdem-3 provides an addi- tional rs-232 interface and windows 3.1 software for showing the demultiplexed lcd signals on a pc. a sim- ple serial interface allows the user to construct a hard- ware demultiplexer for the lcd signals.
pic16f872 ds30221a-page 122 preliminary ? 1999 microchip technology inc. 13.16 picdem-17 the picdem-17 is an evaluation board that demon- strates the capabilities of several microchip microcon- trollers, including pic17c752, pic17c756, pic17c762, and pic17c766. all necessary hardware is included to run basic demo programs, which are sup- plied on a 3.5-inch disk. a programmed sample is included, and the user may erase it and program it with the other sample programs using the pro mate ii or picstart plus device programmers and easily debug and test the sample code. in addition, picdem-17 sup- ports down-loading of programs to and executing out of external flash memory on board. the picdem-17 is also usable with the mplab-ice or picmaster emu- lator, and all of the sample programs can be run and modified using either emulator. additionally, a generous prototype area is available for user hardware. 13.17 seeval evaluation and programming system the seeval seeprom designers kit supports all microchip 2-wire and 3-wire serial eeproms. the kit includes everything necessary to read, write, erase or program special features of any microchip seeprom product including smart serials ? and secure serials. the total endurance ? disk is included to aid in trade- off analysis and reliability calculations. the total kit can significantly reduce time-to-market and result in an optimized system. 13.18 k ee l oq evaluation and programming tools k ee l oq evaluation and programming tools support microchips hcs secure data products. the hcs eval- uation kit includes an lcd display to show changing codes, a decoder to decode transmissions, and a pro- gramming interface to program test transmitters.
? 1999 microchip technology inc. preliminary ds30221a-page 123 pic16f872 table 13-1: development tools from microchip pic12cxxx pic14000 pic16c5x pic16c6x pic16cxxx pic16f62x pic16c7x pic16c7xx pic16c8x pic16f8xx pic16c9xx pic17c4x pic17c7xx pic18cxx2 24cxx/ 25cxx/ 93cxx hcsxxx mcrfxxx mcp2510 software tools mplab ? integrated development environment mplab ? c17 compiler mplab ? c18 compiler mpasm/mplink emulators mplab ? -ice ** picmaster/picmaster-ce icepic ? low-cost in-circuit emulator debugger mplab ? -icd in-circuit debugger * * programmers picstart a plus low-cost universal dev. kit ** pro mate a ii universal programmer ** demo boards and eval kits simice picdem-1 ? picdem-2 ? ? picdem-3 picdem-14a picdem-17 k ee l oq ? evaluation kit k ee l oq transponder kit microid ? programmers kit 125 khz microid developers kit 125 khz anticollision microid developers kit 13.56 mhz anticollision microid developers kit mcp2510 can developers kit * contact the microchip technology inc. web site at www.microchip.com for information on how to use the mplab ? -icd in-circuit debugger (dv164001) with pic16c62, 63, 64, 65, 72, 73, 74, 76, 77 ** contact microchip technology inc. for availability date. ? development tool is available on select devices.
pic16f872 ds30221a-page 124 preliminary ? 1999 microchip technology inc. notes:
? 1999 microchip technology inc. preliminary ds30221a-page 125 pic16f872 14.0 electrical characteristics absolute maximum ratings ? ambient temperature under bias................................................................................................. ............... . -55 to +125c storage temperature ............................................................................................................ .................. -65c to +150c voltage on any pin with respect to v ss (except v dd , mclr . and ra4).......................................... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ............................................................................................................ -0.3 to +7.5v voltage on mclr with respect to v ss (note 2).............................................................................................0 to +13.25v voltage on ra4 with respect to vss ............................................................................................. .....................0 to +8.5v total power dissipation (note 1)............................................................................................... .................................1.0w maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................... ...250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ..................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ............................................................................................................. 20 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................25 ma maximum current sunk by porta and portb (combined) ................................................................................200 ma maximum current sourced by porta and portb (combined) ......................................................................... ..200 ma maximum current sunk by portc.................................................................................................. ......................200 ma maximum current sourced by portc ............................................................................................... ...................200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - ? i oh } + ? {(v dd - v oh ) x i oh } + ? (v o l x i ol ) 2: voltage spikes below v ss at the mclr pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 w should be used when applying a low level to the mclr pin, rather than pulling this pin directly to v ss .. ? notice: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic16f872 ds30221a-page 126 preliminary ? 1999 microchip technology inc. figure 14-1: pic16fxxx voltage-frequency graph figure 14-2: pic16lfxxx voltage-frequency graph frequency voltage 6.0 v 5.5 v 4.5 v 4.0 v 2.0 v 20 mhz 5.0 v 3.5 v 3.0 v 2.5 v frequency voltage 6.0 v 5.5 v 4.5 v 4.0 v 2.0 v 5.0 v 3.5 v 3.0 v 2.5 v equation 1: f max = (6.0 mhz/v) (v ddappmin - 2.0 v) + 4 mhz; v ddappmin = 2.0v - 3.0v note 1: v ddappmin is the minimum voltage of the picmicro ? device in the application. 4 mhz 10 mhz note 2: f max has a maximum frequency of 10mhz. 20 mhz e q u a t i o n 1 e q u a t i o n 2 equation 2: f max = (10.0 mhz/v) (v ddappmin - 3.0 v) + 10 mhz; v ddappmin = 3.0v - 4.0v
? 1999 microchip technology inc. preliminary ds30221a-page 127 pic16f872 14.1 dc characteristics: pic16f872 (industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. characteristic sym min typ? max units conditions d001 d001a supply voltage v dd 4.0 4.5 v bor * - - - 5.5 5.5 5.5 v v v xt, rc and lp osc configuration hs osc configuration bor enabled, fmax = 14mhz (note 7) d002* ram data retention voltage (note 1) v dr -1.5-v d003 v dd start voltage to ensure internal power-on reset signal v por -v ss - v see section on power-on reset for details d004* v dd rise rate to ensure internal power-on reset signal sv dd 0.05 - - v/ms see section on power-on reset for details d005 brown-out reset voltage v bor 3.7 4.0 4.35 v boden bit in configuration word enabled d010 d013 supply current (note 2,5) i dd - - 1.6 7 4 15 ma ma xt, rc osc configuration f osc = 4 mhz, v dd = 5.5v (note 4) hs osc configuration f osc = 20 mhz, v dd = 5.5v d015* brown-out reset current (note 6) d i bor -85200 m a bor enabled v dd = 5.0v d020 d021 d021a power-down current (note 3,5) i pd - - - 10.5 1.5 1.5 42 16 19 m a m a m a v dd = 4.0v, wdt enabled, -40 c to +85 c v dd = 4.0v, wdt disabled, -0 c to +70 c v dd = 4.0v, wdt disabled, -40 c to +85 c d023* brown-out reset current (note 6) d i bor -85200 m a bor enabled v dd = 5.0v legend: * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is mea- sured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc configuration, current through r ext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2r ext (ma) with r ext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 m a to the specification. this value is from character- ization and is for design guidance only. this is not tested. 6: the d current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement. 7: when bor is enabled, the device will operate correctly until the v bor voltage trip point is reached.
pic16f872 ds30221a-page 128 preliminary ? 1999 microchip technology inc. 14.2 dc characteristics: pic16lf872 (industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. characteristic sym min typ? max units conditions d001 supply voltage v dd 2.0 - 5.5 v lp, xt, rc osc configuration (dc - 4 mhz) d002* ram data retention voltage (note 1) v dr -1.5- v d003 v dd start voltage to ensure internal power-on reset signal v por -v ss - v see section on power-on reset for details d004* v dd rise rate to ensure internal power-on reset signal sv dd 0.05 - - v/ms see section on power-on reset for details d005 brown-out reset voltage v bor 3.7 4.0 4.35 v boden bit in configuration word enabled d010 d010a supply current (note 2,5) i dd - - 0.6 20 2.0 35 ma m a xt, rc osc configuration f osc = 4 mhz, v dd = 3.0v (note 4) lp osc configuration f osc = 32 khz, v dd = 3.0v, wdt disabled d015* brown-out reset current (note 6) d i bor -85200 m a bor enabled v dd = 5.0v d020 d021 d021a power-down current (note 3,5) i pd - - - 7.5 0.9 0.9 30 5 5 m a m a m a v dd = 3.0v, wdt enabled, -40 c to +85 c v dd = 3.0v, wdt disabled, 0 c to +70 c v dd = 3.0v, wdt disabled, -40 c to +85 c d023* brown-out reset current (note 6) d i bor -85200 m a bor enabled v dd = 5.0v legend: * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc configuration, current through r ext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2r ext (ma) with r ext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 m a to the specification. this value is from charac- terization and is for design guidance only. this is not tested. 6: the d current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement.
? 1999 microchip technology inc. preliminary ds30221a-page 129 pic16f872 14.3 dc characteristics: pic16f872 and pic16lf872 (industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial operating voltage v dd range as described in dc spec section 14.1 and section 14.2. param no. characteristic sym min typ? max units conditions input low voltage i/o ports v il d030 with ttl buffer v ss - 0.15v dd v for entire v dd range d030a v ss -0.8vv4.5v v dd 5.5v d031 with schmitt trigger buffer v ss -0.2v dd v d032 mclr , osc1 (in rc mode) v ss -0.2v dd v d033 osc1 (in xt, hs and lp) v ss -0.3v dd vnote1 ports rc3 and rc4 d034 with schmitt trigger buffer v ss -0.3v dd v for entire v dd range d034a with smbus -0.5 - 0.6 v for v dd = 4.5 to 5.5v input high voltage i/o ports v ih - d040 with ttl buffer 2.0 - v dd v4.5v v dd 5.5v d040a 0.25v dd + 0.8v -v dd v for entire v dd range d041 with schmitt trigger buffer 0.8v dd -v dd v for entire v dd range d042 mclr 0.8v dd -v dd v d042a osc1 (xt, hs and lp) 0.7v dd -v dd vnote1 d043 osc1 (in rc mode) 0.9v dd -v dd v ports rc3 and rc4 d044 with schmitt trigger buffer 0.7v dd -v dd v for entire v dd range d044a with smbus 1.4 - 5.5 v for v dd = 4.5 to 5.5v d070 portb weak pull-up current i purb 50 250 400 m av dd = 5v, v pin = v ss input leakage current (notes 2, 3) d060 i/o ports i il -- 1 m avss v pin v dd , pin at hi-imped- ance d061 mclr , ra4/t0cki - - 5 m avss v pin v dd d063 osc1 - - 5 m avss v pin v dd , xt, hs and lp osc configuration output low voltage d080 i/o ports v ol --0.6vi ol = 8.5 ma, v dd = 4.5v, -40 c to +85 c d083 osc2/clkout (rc osc config) - - 0.6 v i ol = 1.6 ma, v dd = 4.5v, -40 c to +85 c output high voltage d090 i/o ports (note 3) v oh v dd - 0.7 - - v i oh = -3.0 ma, v dd = 4.5v, -40 c to +85 c d092 osc2/clkout (rc osc config) v dd - 0.7 - - v i oh = -1.3 ma, v dd = 4.5v, -40 c to +85 c legend: * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16f87x be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin.
pic16f872 ds30221a-page 130 preliminary ? 1999 microchip technology inc. d150* open-drain high voltage v od - - 8.5 v ra4 pin -- capacitive loading specs on output pins d100 osc2 pin c osc2 - - 15 pf in xt, hs and lp modes when exter- nal clock is used to drive osc1. d101 d102 all i/o pins and osc2 (in rc mode) scl, sda in i 2 c mode c io c b - - - - 50 400 pf pf data eeprom memory d120 endurance e d 100k - - e/w 25 c at 5v d121 v dd for read/write v drw vmin - 5.5 v using eecon to read/write vmin = min operating voltage d122 erase/write cycle time t dew -48ms program flash memory d130 endurance e p 1000 - - e/w 25 c at 5v d131 v dd for read v pr vmin - 5.5 v vmin = min operating voltage d132a v dd for erase/write vmin - 5.5 v using eecon to read/write, vmin = min operating voltage d133 erase/write cycle time t pew -48ms dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial operating voltage v dd range as described in dc spec section 14.1 and section 14.2. param no. characteristic sym min typ? max units conditions legend: * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16f87x be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin.
? 1999 microchip technology inc. preliminary ds30221a-page 131 pic16f872 14.4 timing parameter symbology the timing parameter symbols have been created fol- lowing one of the following formats: figure 14-3: load conditions 1. tpps2pps 3. t cc : st (i 2 c specifications only) 2. tpps 4. ts (i 2 c specifications only) t ffrequency ttime lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (hi-impedance) v valid l low z hi-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c specifications only) cc hd hold su setup st dat data input hold sto stop condition sta start condition v dd /2 c l r l pin pin v ss v ss c l r l = 464 w c l = 50 pf for all pins except osc2, but including portd and porte outputs as ports 15 pf for osc2 output note: portd and porte are not implemented on the 28-pin devices. load condition 1 load condition 2
pic16f872 ds30221a-page 132 preliminary ? 1999 microchip technology inc. figure 14-4: external clock timing osc1 clkout q4 q1 q2 q3 q4 q1 1 2 3 3 4 4 table 14-1: external clock timing requirements parameter no. sym characteristic min typ? max units conditions f osc external clkin frequency (note 1) dc 4 mhz xt and rc osc mode dc 4 mhz hs osc mode (-04) dc 20 mhz hs osc mode (-20) dc 200 khz lp osc mode oscillator frequency (note 1) dc 4 mhz rc osc mode 0.1 4 mhz xt osc mode 4 5 20 200 mhz khz hs osc mode lp osc mode 1 t osc external clkin period (note 1) 250 ns xt and rc osc mode 250 ns hs osc mode (-04) 50 ns hs osc mode (-20) 5 m s lp osc mode oscillator period (note 1) 250 ns rc osc mode 250 10,000 ns xt osc mode 250 250 ns hs osc mode (-04) 50 250 ns hs osc mode (-20) 5 m s lp osc mode 2 t cy instruction cycle time (note 1) 200 t cy dc ns t cy = 4/f osc 3 to s l , to s h external clock in (osc1) high or low time 100 ns xt oscillator 2.5 m s lp oscillator 15 ns hs oscillator 4 to s r , to s f external clock in (osc1) rise or fall time 25 ns xt oscillator 50 ns lp oscillator 15 ns hs oscillator legend: ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at "min." values with an external clock applied to the osc1/clkin pin. when an external clock input is used, the "max." cycle time limit is "dc" (no clock) for all devices.
? 1999 microchip technology inc. preliminary ds30221a-page 133 pic16f872 figure 14-5: clkout and i/o timing table 14-2: clkout and i/o timing requirements param no. sym characteristic min typ? max units conditions 10* tosh2ckl osc1 - to clkout 75 200 ns note 1 11* tosh2ckh osc1 - to clkout - 75 200 ns note 1 12* tckr clkout rise time 35 100 ns note 1 13* tckf clkout fall time 35 100 ns note 1 14* tckl2iov clkout to port out valid 0.5t cy + 20 ns note 1 15* tiov2ckh port in valid before clkout - t osc + 200 ns note 1 16* tckh2ioi port in hold after clkout - 0 ns note 1 17* tosh2iov osc1 - (q1 cycle) to port out valid 100 255 ns 18* tosh2ioi osc1 - (q2 cycle) to port input invalid (i/o in hold time) standard ( f ) 100 ns extended ( lf ) 200 ns 19* tiov2osh port input valid to osc1 - (i/o in setup time) 0 ns 20* tior port output rise time standard ( f ) 10 40 ns extended ( lf ) 145 ns 21* tiof port output fall time standard ( f ) 10 40 ns extended ( lf ) 145 ns 22??* tinp int pin high or low time t cy ns 23??* trbp rb7:rb4 change int high or low time t cy ns legend: * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. ?? these parameters are asynchronous events not related to any internal clock edges. note 1: measurements are taken in rc mode where clkout output is 4 x t osc . note: refer to figure 14-3 for load conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value
pic16f872 ds30221a-page 134 preliminary ? 1999 microchip technology inc. figure 14-6: reset, watchdog timer, oscillator start-up timer and power-up timer timing figure 14-7: brown-out reset timing table 14-3: reset, watchdog timer, oscillator start-up timer, power-up timer, and brown-out reset requirements parameter no. sym characteristic min typ? max units conditions 30 tmcl mclr pulse width (low) 2 m sv dd = 5v, -40c to +85c 31* twdt watchdog timer time-out period (no prescaler) 71833msv dd = 5v, -40c to +85c 32 tost oscillation start-up timer period 1024 t osc t osc = osc1 period 33* tpwrt power up timer period 28 72 132 ms v dd = 5v, -40c to +85c 34 t ioz i/o hi-impedance from mclr low or watchdog timer reset 2.1 m s 35 t bor brown-out reset pulse width 100 m sv dd v bor (d005) legend: * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 14-3 for load conditions. v dd v bor 35
? 1999 microchip technology inc. preliminary ds30221a-page 135 pic16f872 figure 14-8: timer0 and timer1 external clock timings table 14-4: timer0 and timer1 external clock requirements param no. sym characteristic min typ? max units conditions 40* tt0h t0cki high pulse width no prescaler 0.5t cy + 20 ns must also meet parameter 42 with prescaler 10 ns 41* tt0l t0cki low pulse width no prescaler 0.5t cy + 20 ns must also meet parameter 42 with prescaler 10 ns 42* tt0p t0cki period no prescaler t cy + 40 ns with prescaler greater of: 20 or t cy + 40 n ns n = prescale value (2, 4, ..., 256) 45* tt1h t1cki high time synchronous, prescaler = 1 0.5t cy + 20 ns must also meet parameter 47 synchronous, prescaler = 2,4,8 standard( f )15ns extended( lf )25ns asynchronous standard( f )30ns extended( lf )50ns 46* tt1l t1cki low time synchronous, prescaler = 1 0.5t cy + 20 ns must also meet parameter 47 synchronous, prescaler = 2,4,8 standard( f )15ns extended( lf )25ns asynchronous standard( f )30ns extended( lf )50ns 47* tt1p t1cki input period synchronous standard( f ) greater of : 30 or t cy + 40 n ns n = prescale value (1, 2, 4, 8) extended( lf ) greater of : 50 or t cy + 40 n n = prescale value (1, 2, 4, 8) asynchronous standard( f )60ns extended( lf )100ns ft1 timer1 oscillator input frequency range (oscillator enabled by setting bit t1oscen) dc 200 khz 48 tckeztmr1 delay from external clock edge to timer increment 2tosc 7tosc * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 14-3 for load conditions. 46 47 45 48 41 42 40 ra4/t0cki rc0/t1oso/t1cki tmr0 or tmr1
pic16f872 ds30221a-page 136 preliminary ? 1999 microchip technology inc. figure 14-9: capture/compare/pwm timings (ccp1) table 14-5: capture/compare/pwm requirements (ccp1) param no. sym characteristic min typ? max units conditions 50* tccl ccp1 input low time no prescaler 0.5t cy + 20 ns with prescaler standard( f ) 10 ns extended( lf )20ns 51* tcch ccp1 input high time no prescaler 0.5t cy + 20 ns with prescaler standard( f )10ns extended( lf )20ns 52* tccp ccp1 input period 3t cy + 40 n ns n = prescale value (1,4 or 16) 53* tccr ccp1 output rise time standard( f ) 10 25 ns extended( lf ) 25 50 ns 54* tccf ccp1 output fall time standard( f ) 10 25 ns extended( lf ) 25 45 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 14-3 for load conditions. rc2/ccp1 (capture mode) 50 51 52 53 54 rc2/ccp1 (compare or pwm mode)
? 1999 microchip technology inc. preliminary ds30221a-page 137 pic16f872 figure 14-10: spi master mode timing (cke = 0, smp = 0) figure 14-11: spi master mode timing (cke = 1, smp = 1) ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 78 79 80 79 78 msb lsb bit6 - - - - - -1 msb in lsb in bit6 - - - -1 note: refer to figure 14-3 for load conditions. ss sck (ckp = 0) sck (ckp = 1) sdo sdi 81 71 72 74 75, 76 78 80 msb 79 73 msb in bit6 - - - - - -1 lsb in bit6 - - - -1 lsb note: refer to figure 14-3 for load conditions.
pic16f872 ds30221a-page 138 preliminary ? 1999 microchip technology inc. figure 14-12: spi slave mode timing (cke = 0) figure 14-13: spi slave mode timing (cke = 1) ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78 sdi msb lsb bit6 - - - - - -1 msb in bit6 - - - -1 lsb in 83 note: refer to figure 14-3 for load conditions. ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 82 sdi 74 75, 76 msb bit6 - - - - - -1 lsb 77 msb in bit6 - - - -1 lsb in 80 83 note: refer to figure 14-3 for load conditions.
? 1999 microchip technology inc. preliminary ds30221a-page 139 pic16f872 table 14-6: spi mode requirements figure 14-14: i 2 c bus start/stop bits timing table 14-7: i 2 c bus start/stop bits requirements param no. sym characteristic min typ? max units conditions 70* tssl2sch, tssl2scl ss to sck or sck - input t cy ns 71* tsch sck input high time (slave mode) t cy + 20 ns 72* tscl sck input low time (slave mode) t cy + 20 ns 73* tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ns 74* tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ns 75* tdor sdo data output rise time standard( f ) extended( lf ) 10 25 25 50 ns ns 76* tdof sdo data output fall time 10 25 ns 77* tssh2doz ss - to sdo output hi-impedance 10 50 ns 78* tscr sck output rise time (master mode) standard( f ) extended( lf ) 10 25 25 50 ns ns 79* tscf sck output fall time (master mode) 10 25 ns 80* tsch2dov, tscl2dov sdo data output valid after sck edge standard( f ) extended( lf ) 50 145 ns 81* tdov2sch, tdov2scl sdo data output setup to sck edge t cy ns 82* tssl2dov sdo data output valid after ss edge 50 ns 83* tsch2ssh, tscl2ssh ss - after sck edge 1.5t cy + 40 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. parameter no. sym characteristic min typ max units conditions 90 t su : sta start condition 100 khz mode 4700 ns only relevant for repeated start condition setup time 400 khz mode 600 91 t hd : sta start condition 100 khz mode 4000 ns after this period the first clock pulse is generated hold time 400 khz mode 600 92 t su : sto stop condition 100 khz mode 4700 ns setup time 400 khz mode 600 93 t hd : sto stop condition 100 khz mode 4000 ns hold time 400 khz mode 600 note: refer to figure 14-3 for load conditions. 91 93 scl sda start condition stop condition 90 92
pic16f872 ds30221a-page 140 preliminary ? 1999 microchip technology inc. figure 14-15: i 2 c bus data timing table 14-8: i 2 c bus data requirements param no. sym characteristic min max units conditions 100 t high clock high time 100 khz mode 4.0 m s device must operate at a mini- mum of 1.5 mhz 400 khz mode 0.6 m s device must operate at a mini- mum of 10 mhz ssp module 1.5t cy 101 t low clock low time 100 khz mode 4.7 m s device must operate at a mini- mum of 1.5 mhz 400 khz mode 1.3 m s device must operate at a mini- mum of 10 mhz ssp module 1.5t cy 102 t r sda and scl rise time 100 khz mode 1000 ns 400 khz mode 20 + 0.1cb 300 ns cb is specified to be from 10 to 400 pf 103 t f sda and scl fall time 100 khz mode 300 ns 400 khz mode 20 + 0.1cb 300 ns cb is specified to be from 10 to 400 pf 90 t su : sta start condition setup time 100 khz mode 4.7 m s only relevant for repeated start condition 400 khz mode 0.6 m s 91 t hd : sta start condition hold time 100 khz mode 4.0 m s after this period the first clock pulse is generated 400 khz mode 0.6 m s 106 t hd : dat data input hold time 100 khz mode 0 ns 400 khz mode 0 0.9 m s 107 t su : dat data input setup time 100 khz mode 250 ns note 2 400 khz mode 100 ns 92 t su : sto stop condition setup time 100 khz mode 4.7 m s 400 khz mode 0.6 m s 109 t aa output valid from clock 100 khz mode 3500 ns note 1 400 khz mode ns 110 t buf bus free time 100 khz mode 4.7 m s time the bus must be free before a new transmission can start 400 khz mode 1.3 m s cb bus capacitive loading 400 pf note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast-mode (400 khz) i 2 c-bus device can be used in a standard-mode (100 khz) i 2 c-bus system, but the requirement tsu; dat 3 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max.+tsu; dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c bus specification) before the scl line is released. note: refer to figure 14-3 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
? 1999 microchip technology inc. preliminary ds30221a-page 141 pic16f872 table 14-9: pic16f872 and pic16lf872 (industrial) param no. sym characteristic min typ? max units conditions a01 n r resolution 10-bits bit v ref = v dd = 5.12v, v ss v ain v ref a03 e il integral linearity error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a04 e dl differential linearity error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a06 e off offset error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a07 e gn gain error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a10 monotonicity (3) guaranteed v ss v ain v ref a20 v ref reference voltage (v ref + - v ref -) 2.0v v dd + 0.3 v absolute minimum electrical spec. to ensure 10-bit accuracy. a21 v ref + reference voltage high av dd - 2.5v av dd + 0.3v v a22 v ref - reference voltage low av ss - 0.3v v ref + - 2.0v v a25 v ain analog input voltage v ss - 0.3 v ref + 0.3 v a30 z ain recommended impedance of analog voltage source 10.0 k w a40 i ad a/d conversion cur- rent (v dd ) standard 220 m a average current consumption when a/d is on. (note 1) extended 90 m a a50 i ref v ref input current (note 2) 10 1000 10 m a m a during v ain acquisition. based on differential of v hold to v ain to charge c hold , see section 10.1. during a/d conversion cycle * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: when a/d is off, it will not consume any current other than minor leakage current. the power-down current spec includes any such leakage from the a/d module. 2: v ref current is from ra3 pin or v dd pin, whichever is selected as reference input. 3: the a/d conversion result never decreases with an increase in the input voltage, and has no missing codes.
pic16f872 ds30221a-page 142 preliminary ? 1999 microchip technology inc. figure 14-16: a/d conversion timing table 14-10: a/d conversion requirements param no. sym characteristic min typ? max units conditions 130 t ad a/d clock period standard( f ) 1.6 m st osc based, v ref 3 3.0v extended( lf )3.0 m st osc based, v ref 3 2.0v standard( f ) 2.0 4.0 6.0 m s a/d rc mode extended( lf ) 3.0 6.0 9.0 m s a/d rc mode 131 t cnv conversion time (not including s/h time) (note 1) 12t ad 132 t acq acquisition time note 2 10* 40 m s m s the minimum time is the ampli- fier settling time. this may be used if the "new" input voltage has not changed by more than 1 lsb (i.e., 20.0 mv @ 5.12v) from the last sampled voltage (as stated on c hold ). 134 t go q4 to a/d clock start t osc /2 if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. this specification ensured by design. note 1: adres register may be read on the following t cy cycle. 2: see section 10.1 for min conditions. 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data (t osc /2) (1) 987 210 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 1 t cy . . . . . .
? 1999 microchip technology inc. preliminary ds30221a-page 143 pic16f872 15.0 dc and ac characteristics graphs and tables the graphs and tables provided in this section are for design guidance and are not tested . in some graphs or tables, the data presented are out- side specified operating range (i.e., outside specified v dd range). this is for information only and devices are ensured to operate properly only within the speci- fied range. the data presented in this section is a statistical sum- mary of data collected on units from different lots over a period of time and matrix samples. 'typical' repre- sents the mean of the distribution at 25 c. 'max' or 'min' represents (mean + 3 s ) or (mean - 3 s ) respectively, where s is standard deviation, over the whole temper- ature range. graphs and tables not available at this time.
pic16f872 ds30221a-page 144 preliminary ? 1999 microchip technology inc. notes:
? 1999 microchip technology inc. preliminary ds30221a-page 145 pic16f872 16.0 packaging information 16.1 package marking information 28-lead soic yywwnnn example pic16f872-i/so xxxxxxxxxxxxxxxxx yywwnnn 28-lead pdip (skinny dip) example pic16f872-i/sp 9910saa 9910saa legend: mm...m microchip part number information xx...x customer specific information* yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * standard otp marking consists of microchip part number, year code, week code, facility code, mask rev#, and assembly code. for otp marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price. xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx 28-lead ssop yywwnnn example pic16f872-i/ss 9910saa xxxxxxxxxxxx xxxxxxxxxxxx
pic16f872 ds30221a-page 146 preliminary ? 1999 microchip technology inc. 28-lead plastic shrink small outline (ss) C 209 mil, 5.30 mm (ssop) *controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 (0.254mm) per side. jedec equivalent: ms-150 drawing no. c04-073 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 a mold draft angle top 0.38 0.32 0.25 .015 .013 .010 b lead width 203.20 101.60 0.00 8 4 0 f foot angle 0.25 0.18 0.10 .010 .007 .004 c lead thickness 0.94 0.75 0.56 .037 .030 .022 l foot length 10.34 10.20 10.06 .407 .402 .396 d overall length 5.38 5.25 5.11 .212 .207 .201 e1 molded package width 8.10 7.85 7.59 .319 .309 .299 e overall width 0.25 0.15 0.05 .010 .006 .002 a1 standoff 1.83 1.73 1.63 .072 .068 .064 a2 molded package thickness 1.98 1.85 1.73 .078 .073 .068 a overall height 0.65 .026 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters* inches units 2 1 d p n b e1 e l b c f a a2 a1 a b
? 1999 microchip technology inc. preliminary ds30221a-page 147 pic16f872 28-lead skinny plastic dual in-line (sp) C 300 mil (pdip) 15 10 5 15 10 5 b mold draft angle bottom 15 10 5 15 10 5 a mold draft angle top 10.92 8.89 8.13 .430 .350 .320 eb overall row spacing 0.56 0.48 0.41 .022 .019 .016 b lower lead width 1.65 1.33 1.02 .065 .053 .040 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.18 .135 .130 .125 l tip to seating plane 35.18 34.67 34.16 1.385 1.365 1.345 d overall length 7.49 7.24 6.99 .295 .285 .275 e1 molded package width 8.26 7.87 7.62 .325 .310 .300 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 3.43 3.30 3.18 .135 .130 .125 a2 molded package thickness 4.06 3.81 3.56 .160 .150 .140 a top to seating plane 2.54 .100 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n e1 c eb b e a p l a2 b b1 a a1 notes: jedec equivalent: mo-095 drawing no. c04-070 *controlling parameter dimension d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 (0.254mm) per side.
pic16f872 ds30221a-page 148 preliminary ? 1999 microchip technology inc. 28-lead plastic small outline (so) C wide, 300 mil (soic) foot angle top f 048048 15 12 0 15 12 0 b mold draft angle bottom 15 12 0 15 12 0 a mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.33 0.28 0.23 .013 .011 .009 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.74 0.50 0.25 .029 .020 .010 h chamfer distance 18.08 17.87 17.65 .712 .704 .695 d overall length 7.59 7.49 7.32 .299 .295 .288 e1 molded package width 10.67 10.34 10.01 .420 .407 .394 e overall width 0.30 0.20 0.10 .012 .008 .004 a1 standoff 2.39 2.31 2.24 .094 .091 .088 a2 molded package thickness 2.64 2.50 2.36 .104 .099 .093 a overall height 1.27 .050 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d p n b e e1 l c b 45 h f a2 a a a1 *controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 (0.254mm) per side. jedec equivalent: ms-013 drawing no. c04-052
? 1999 microchip technology inc. preliminary ds30221a-page 149 pic16f872 appendix a: revision history appendix b: conversion considerations considerations for converting from previous versions of devices to the ones listed in this data sheet are listed in table b-1. version date revision description a 1999 this is a new data sheet. however, these devices are similar to the pic16c72a devices found in the pic16c62b/72a data sheet (ds35008a). table b-1: conversion considerations characteristic pic16c72a pic16f872 pins 28 28 timers 3 3 interrupts 8 10 communication ssp (spi, i 2 c slave) ssp (spi, i 2 c master/slave) frequency 20 mhz 20 mhz a/d 8-bit 10-bit ccp 1 1 program memory 2k eprom 2k flash ram 128 bytes 128 bytes eeprom data none 64 bytes other ? in-circuit debugger, low voltage programming
pic16f872 ds30221a-page 150 preliminary ? 1999 microchip technology inc. notes:
pic16f872 ? 1999 microchip technology inc. ds30221a-page 151 index a a/d ..................................................................................... 85 adcon0 register ...................................................... 85 adcon1 register ...................................................... 86 adif bit ...................................................................... 87 analog input model block diagram ............................ 89 analog port pins .......................................................... 6 block diagram ............................................................ 88 configuring analog port pins ..................................... 90 configuring the interrupt ............................................ 87 configuring the module .............................................. 87 conversion clock ....................................................... 90 conversions ............................................................... 91 delays ........................................................................ 89 effects of a reset ....................................................... 92 go/done bit ............................................................. 87 internal sampling switch (rss) impedence ............... 88 operation during sleep ............................................. 92 sampling requirements ............................................. 88 source impedence ..................................................... 88 time delays ............................................................... 89 absolute maximum ratings ............................................. 125 ack .................................................................................... 62 acknowledge data bit ........................................................ 56 acknowledge pulse ............................................................ 62 acknowledge sequence enable bit ................................... 56 acknowledge status bit ...................................................... 56 adres register ............................................................ 9, 85 application note an578, "use of the ssp module in the i2c multi-master environment." ............................... 61 application notes an552 (implementing wake-up on key strokes using pic16cxxx) .................................................... 25 an556 (table reading using pic16cxx) ................. 20 architecture pic16f872 block diagram .......................................... 5 assembler mpasm assembler .................................................. 119 b banking, data memory .................................................. 7, 12 baud rate generator ......................................................... 68 bclif ................................................................................. 18 bf .................................................................... 54, 62, 71, 73 block diagrams a/d ............................................................................. 88 analog input model .................................................... 89 baud rate generator ................................................. 68 capture ...................................................................... 48 compare .................................................................... 49 i 2 c master mode ........................................................ 66 i 2 c module ................................................................. 61 pwm .......................................................................... 49 ssp (i 2 c mode) ......................................................... 61 ssp (spi mode) ......................................................... 57 timer0/wdt prescaler .............................................. 37 timer2 ........................................................................ 45 brg ................................................................................... 68 brown-out reset (bor) ............................... 95, 99, 101, 102 bor status (bor bit) ................................................ 19 buffer full bit, bf ............................................................... 62 buffer full status bit, bf .................................................... 54 bus arbitration ................................................................... 78 bus collision during a restart condition ...................... 81 bus collision during a start condition ............................... 79 bus collision during a stop condition ............................... 82 bus collision interrupt flag bit, bclif ............................... 18 bus collision section ......................................................... 78 c capture/compare/pwm capture block diagram ................................................... 48 ccp1con register ........................................... 47 ccp1if .............................................................. 48 mode ................................................................. 48 prescaler ........................................................... 48 ccp timer resources ............................................... 47 compare block diagram ................................................... 49 mode ................................................................. 49 software interrupt mode .................................... 49 special event trigger ........................................ 49 special trigger output of ccp1 ........................ 49 section ....................................................................... 47 special event trigger and a/d conversions ............. 49 capture/compare/pwm (ccp) ccp1 rc2/ccp1 pin ..................................................... 6 pwm block diagram ................................................. 49 pwm mode ................................................................ 49 ccp1con ......................................................................... 11 ccp1m0 bit ....................................................................... 47 ccp1m1 bit ....................................................................... 47 ccp1m2 bit ....................................................................... 47 ccp1m3 bit ....................................................................... 47 ccp1x bit .......................................................................... 47 ccp1y bit .......................................................................... 47 ccpr1h register .................................................... 9, 11, 47 ccpr1l register ........................................................ 11, 47 cke ................................................................................... 54 ckp ................................................................................... 55 clock polarity select bit, ckp ............................................ 55 code examples indirect addressing .................................................... 20 code protection ......................................................... 95, 109 computed goto ............................................................... 20 configuration bits .............................................................. 95 conversion considerations .............................................. 149 d d/a ..................................................................................... 54 data memory ....................................................................... 7 bank select (rp1:rp0 bits) .................................. 7, 12 general purpose registers ......................................... 7 register file map ........................................................ 8 special function registers .......................................... 9 data/address bit, d/a ........................................................ 54 dc characteristics ........................................................... 127 development support ...................................................... 119 device overview .................................................................. 5 direct addressing .............................................................. 21 e electrical characteristics ................................................. 125 errata ................................................................................... 3 f firmware instructions ...................................................... 111 fsr register ..................................................... 9, 10, 11, 20
pic16f872 ds30221a-page 152 ? 1999 microchip technology inc. g general call address sequence ........................................ 64 general call address support ........................................... 64 general call enable bit ...................................................... 56 i i/o ports ............................................................................. 23 i 2 c ...................................................................................... 61 i 2 c master mode reception ............................................... 73 i 2 c master mode restart condition ................................... 70 i 2 c mode selection ............................................................ 61 i 2 c module acknowledge sequence timing .................................. 75 addressing ................................................................. 62 baud rate generator ................................................. 68 block diagram ............................................................ 66 brg block diagram ................................................... 68 brg reset due to sda collision ............................... 80 brg timing ............................................................... 68 bus arbitration ........................................................... 78 bus collision .............................................................. 78 acknowledge ...................................................... 78 restart condition ............................................... 81 restart condition timing (case1) ...................... 81 restart condition timing (case2) ...................... 81 start condition ................................................... 79 start condition timing ................................. 79, 80 stop condition ................................................... 82 stop condition timing (case1) .......................... 82 stop condition timing (case2) .......................... 82 transmit timing ................................................. 78 bus collision timing .................................................... 78 clock arbitration ......................................................... 77 clock arbitration timing (master transmit) ................ 77 conditions to not give ack pulse .............................. 62 general call address support ................................... 64 master mode .............................................................. 66 master mode 7-bit reception timing .......................... 74 master mode operation ............................................. 67 master mode start condition ..................................... 69 master mode transmission ........................................ 71 master mode transmit sequence .............................. 67 multi-master communication ..................................... 78 multi-master mode ..................................................... 67 operation ................................................................... 61 repeat start condition timing .................................... 70 slave mode ................................................................ 62 slave reception ......................................................... 63 slave transmission .................................................... 63 sspbuf ..................................................................... 62 stop condition receive or transmit timing ................ 76 stop condition timing ................................................. 76 waveforms for 7-bit reception .................................. 63 waveforms for 7-bit transmission ............................. 64 i 2 c module address register, sspadd ............................ 62 i 2 c slave mode .................................................................. 62 id locations ............................................................... 95, 109 in-circuit serial programming (icsp) ........................ 95, 110 indf ................................................................................... 11 indf register .......................................................... 9, 10, 20 indirect addressing ...................................................... 20, 21 fsr register ............................................................... 7 instruction format ............................................................ 111 instruction set .................................................................. 111 addlw .................................................................... 113 addwf .................................................................... 113 andlw .................................................................... 113 andwf .................................................................... 113 bcf ......................................................................... 113 bsf .......................................................................... 113 btfsc ..................................................................... 114 btfss ..................................................................... 114 call ........................................................................ 114 clrf ....................................................................... 114 clrw ...................................................................... 114 clrwdt ................................................................. 114 comf ...................................................................... 115 decf ....................................................................... 115 decfsz .................................................................. 115 goto ...................................................................... 115 incf ........................................................................ 115 incfsz .................................................................... 115 iorlw ..................................................................... 116 iorwf ..................................................................... 116 movf ...................................................................... 116 movlw ................................................................... 116 movwf ................................................................... 116 nop ......................................................................... 116 retfie .................................................................... 117 retlw .................................................................... 117 return .................................................................. 117 rlf .......................................................................... 117 rrf ......................................................................... 117 sleep ..................................................................... 117 sublw .................................................................... 118 subwf .................................................................... 118 swapf .................................................................... 118 xorlw ................................................................... 118 xorwf ................................................................... 118 summary table ....................................................... 112 intcon ............................................................................. 11 intcon register ............................................................... 14 gie bit ....................................................................... 14 inte bit ..................................................................... 14 intf bit ..................................................................... 14 peie bit ..................................................................... 14 rbie bit ..................................................................... 14 rbif bit ............................................................... 14, 25 t0ie bit ...................................................................... 14 t0if bit ...................................................................... 14 inter-integrated circuit (i 2 c) .............................................. 53 internal sampling switch (rss) impedence ....................... 88 interrupt sources ....................................................... 95, 105 block diagram ......................................................... 105 interrupt on change (rb7:rb4 ) ............................... 25 rb0/int pin, external .......................................... 6, 106 tmr0 overflow ........................................................ 106 interrupts bus collision interrupt ................................................ 18 synchronous serial port interrupt .............................. 16 interrupts, context saving during .................................... 106 interrupts, enable bits global interrupt enable (gie bit) ....................... 14, 105 interrupt on change (rb7:rb4) enable (rbie bit) ........................................................... 14, 106 peripheral interrupt enable (peie bit) ....................... 14 rb0/int enable (inte bit) ........................................ 14 tmr0 overflow enable (t0ie bit) ............................. 14
pic16f872 ? 1999 microchip technology inc. ds30221a-page 153 interrupts, flag bits interrupt on change (rb7:rb4) flag (rbif bit) ..................................................... 14, 25, 106 rb0/int flag (intf bit) ............................................. 14 tmr0 overflow flag (t0if bit) .......................... 14, 106 k keeloq evaluation and programming tools ................. 122 l loading of pc .................................................................... 20 m master clear (mclr ) ........................................................... 6 mclr reset, normal operation ................ 99, 101, 102 mclr reset, sleep ................................. 99, 101, 102 memory organization data memory ............................................................... 7 program memory ......................................................... 7 mplab integrated development environment software . 119 multi-master communication ............................................. 78 multi-master mode ............................................................. 67 o opcode field descriptions ............................................ 111 option ............................................................................. 11 option_reg register ..................................................... 13 intedg bit ................................................................ 13 ps2:ps0 bits ............................................................. 13 psa bit ....................................................................... 13 rbpu bit .................................................................... 13 t0cs bit ..................................................................... 13 t0se bit ..................................................................... 13 osc1/clkin pin ................................................................. 6 osc2/clkout pin ............................................................. 6 oscillator configuration ................................................ 95, 97 hs ...................................................................... 97, 101 lp ....................................................................... 97, 101 rc ................................................................ 97, 98, 101 xt ...................................................................... 97, 101 oscillator, wdt ................................................................ 107 output of tmr2 ................................................................. 45 p p (stop bit) ......................................................................... 54 packaging ........................................................................ 145 paging, program memory .............................................. 7, 20 pcl register ...................................................... 9, 10, 11, 20 pclath register .............................................. 9, 10, 11, 20 pcon register .................................................... 11, 19, 100 bor bit ...................................................................... 19 por bit ...................................................................... 19 picdem-1 low-cost picmicro demo board ................... 121 picdem-2 low-cost pic16cxx demo board ................ 121 picdem-3 low-cost pic16cxxx demo board .............. 121 picstart plus entry level development system ...... 121 pie1 register ............................................................... 11, 15 pie2 register ............................................................... 11, 17 pinout descriptions pic16f872 ................................................................... 6 pir1 register ..................................................................... 16 pir2 register ..................................................................... 18 pop ................................................................................... 20 porta .......................................................................... 6, 11 analog port pins .......................................................... 6 initialization ................................................................ 23 porta register ........................................................ 23 ra3, ra0 and ra5 port pins .................................... 23 ra4/t0cki pin ...................................................... 6, 23 ra5/ss /an4 pin .......................................................... 6 trisa register .......................................................... 23 porta register .................................................................. 9 portb .......................................................................... 6, 11 portb register ........................................................ 25 pull-up enable (rbpu bit) ......................................... 13 rb0/int edge select (intedg bit) .......................... 13 rb0/int pin, external ......................................... 6, 106 rb3:rb0 port pins .................................................... 25 rb7:rb4 interrupt on change ................................. 106 rb7:rb4 interrupt on change enable (rbie bit) ........................................................... 14, 106 rb7:rb4 interrupt on change flag (rbif bit) ..................................................... 14, 25, 106 rb7:rb4 port pins .................................................... 25 trisb register .......................................................... 25 portb register .................................................................. 9 portc .......................................................................... 6, 11 block diagram ........................................................... 27 portc register ........................................................ 27 rc0/t1oso/t1cki pin ............................................... 6 rc1/t1osi pin ............................................................ 6 rc2/ccp1 pin ............................................................. 6 rc3/sck/scl pin ....................................................... 6 rc4/sdi/sda pin ........................................................ 6 rc5/sdo pin .............................................................. 6 rc6 pin ....................................................................... 6 rc7 pin ....................................................................... 6 trisc register ......................................................... 27 portc register .................................................................. 9 postscaler, wdt assignment (psa bit) ................................................ 13 rate select (ps2:ps0 bits) ....................................... 13 power-on reset (por) ........................ 95, 99, 100, 101, 102 oscillator start-up timer (ost) ......................... 95, 100 por status (por bit) ............................................... 19 power control (pcon) register .............................. 100 power-down (pd bit) ........................................... 12, 99 power-up timer (pwrt) ................................... 95, 100 time-out (to bit) ................................................. 12, 99 time-out sequence on power-up .................... 103, 104 pr2 .................................................................................... 11 pr2 register ............................................................... 10, 45 prescaler, timer0 assignment (psa bit) ................................................ 13 rate select (ps2:ps0 bits) ....................................... 13 pro mate ii universal programmer ........................... 121 product identification system .......................................... 158 program counter reset conditions ..................................................... 101 program memory ................................................................. 7 interrupt vector ............................................................ 7 paging ................................................................... 7, 20 program memory map ................................................. 7 reset vector ................................................................ 7 program verification ........................................................ 109 programming pin (v pp ) ....................................................... 6 programming, device instructions ................................... 111 push ................................................................................. 20
pic16f872 ds30221a-page 154 ? 1999 microchip technology inc. r r/w .................................................................................... 54 r/w bit ............................................................................... 62 r/w bit ............................................................................... 63 read/write bit, r/w ........................................................... 54 receive enable bit ............................................................. 56 receive overflow indicator bit, sspov ............................. 55 register file ......................................................................... 7 register file map ................................................................. 8 registers fsr summary ........................................................... 11 indf summary .......................................................... 11 intcon summary ..................................................... 11 option summary ..................................................... 11 pcl summary ............................................................ 11 pclath summary .................................................... 11 portb summary ...................................................... 11 sspstat ................................................................... 54 status summary .................................................... 11 summary ...................................................................... 9 tmr0 summary ......................................................... 11 trisb summary ........................................................ 11 reset ............................................................................ 95, 99 block diagram ............................................................ 99 reset conditions for all registers ........................... 102 reset conditions for pcon register ....................... 101 reset conditions for program counter .................... 101 reset conditions for status register ................... 101 restart condition enabled bit ............................................ 56 revision history ............................................................... 149 s s (start bit) ......................................................................... 54 sck .................................................................................... 57 scl .................................................................................... 62 sda .................................................................................... 62 sdi ..................................................................................... 57 sdo ................................................................................... 57 seeval evaluation and programming system ............ 122 serial clock, sck ............................................................... 57 serial clock, scl ............................................................... 62 serial data address, sda .................................................. 62 serial data in, sdi ............................................................. 57 serial data out, sdo ......................................................... 57 slave select, ss ................................................................ 57 sleep .................................................................. 95, 99, 108 smp ................................................................................... 54 software simulator (mplab-sim) .................................... 120 special features of the cpu .............................................. 95 special function registers .................................................. 9 speed, operating ................................................................. 1 spi master mode .............................................................. 58 master mode timing .................................................. 58 serial clock ................................................................ 57 serial data in ............................................................. 57 serial data out .......................................................... 57 serial peripheral interface (spi) ................................ 53 slave mode timing .................................................... 59 slave mode timing diagram ...................................... 59 slave select ............................................................... 57 spi clock .................................................................... 58 spi mode ................................................................... 57 spi clock edge select, cke .............................................. 54 spi data input sample phase select, smp ....................... 54 spi module slave mode ................................................................ 59 ss ...................................................................................... 57 ssp .................................................................................... 53 block diagram (spi mode) ........................................ 57 ra5/ss /an4 pin .......................................................... 6 rc3/sck/scl pin ....................................................... 6 rc4/sdi/sda pin ........................................................ 6 rc5/sdo pin ............................................................... 6 spi mode ................................................................... 57 sspadd .................................................................... 62 sspbuf .............................................................. 58, 62 sspcon1 ................................................................. 55 sspcon2 ................................................................. 56 sspsr ................................................................ 58, 62 sspstat ............................................................ 54, 62 ssp i 2 c ssp i 2 c operation .................................................... 61 ssp module spi master mode ....................................................... 58 spi slave mode ......................................................... 59 sspcon1 register ................................................... 61 ssp overflow detect bit, sspov ...................................... 62 sspadd register ........................................................ 10, 11 sspbuf ...................................................................... 11, 62 sspbuf register ................................................................ 9 sspcon register ............................................................... 9 sspcon1 .................................................................... 55, 61 sspcon2 .......................................................................... 56 sspen ............................................................................... 55 sspif .......................................................................... 16, 63 sspm3:sspm0 ................................................................. 55 sspov .................................................................. 55, 62, 73 sspstat .............................................................. 11, 54, 62 sspstat register ............................................................ 10 stack .................................................................................. 20 overflows ................................................................... 20 underflow .................................................................. 20 start bit (s) ......................................................................... 54 start condition enabled bit ................................................ 56 status register ........................................................ 11, 12 c bit ........................................................................... 12 dc bit ........................................................................ 12 irp bit ....................................................................... 12 pd bit .................................................................. 12, 99 rp1:rp0 bits ............................................................. 12 to bit .................................................................. 12, 99 z bit ........................................................................... 12 stop bit (p) ......................................................................... 54 stop condition enable bit .................................................. 56 synchronous serial port .................................................... 53 synchronous serial port enable bit, sspen ..................... 55 synchronous serial port interrupt ...................................... 16 synchronous serial port mode select bits, sspm3:sspm0 ................................................................. 55 t t1ckps0 bit ...................................................................... 41 t1ckps1 bit ...................................................................... 41 t1con ............................................................................... 11 t1con register .......................................................... 11, 41 t1oscen bit ..................................................................... 41 t1sync bit ........................................................................ 41 t2ckps0 bit ...................................................................... 45 t2ckps1 bit ...................................................................... 45 t2con register .......................................................... 11, 45
pic16f872 ? 1999 microchip technology inc. ds30221a-page 155 t ad ..................................................................................... 90 timer0 clock source edge select (t0se bit) ........................ 13 clock source select (t0cs bit) ................................. 13 overflow enable (t0ie bit) ........................................ 14 overflow flag (t0if bit) ..................................... 14, 106 overflow interrupt .................................................... 106 ra4/t0cki pin, external clock ................................... 6 timer1 ................................................................................ 41 rc0/t1oso/t1cki pin ............................................... 6 rc1/t1osi pin ............................................................ 6 timers timer0 external clock .................................................... 38 interrupt ............................................................. 37 prescaler ............................................................ 38 prescaler block diagram ................................... 37 section ............................................................... 37 t0cki ................................................................. 38 timer1 asynchronous counter mode ............................ 43 capacitor selection ............................................ 43 operation in timer mode ................................... 42 oscillator ............................................................ 43 prescaler ............................................................ 43 resetting of timer1 registers ........................... 43 resetting timer1 using a ccp trigger output .. 43 synchronized counter mode ............................. 42 t1con ............................................................... 41 tmr1h .............................................................. 43 tmr1l ............................................................... 43 timer2 block diagram ................................................... 45 postscaler .......................................................... 45 prescaler ............................................................ 45 t2con ............................................................... 45 timing diagrams a/d conversion ........................................................ 142 acknowledge sequence timing ................................. 75 baud rate generator with clock arbitration .............. 68 brg reset due to sda collision .............................. 80 brown-out reset ...................................................... 134 bus collision start condition timing ....................................... 79 bus collision during a restart condition (case 1) .... 81 bus collision during a restart condition (case2) ..... 81 bus collision during a start condition (scl = 0) ...... 80 bus collision during a stop condition ....................... 82 bus collision for transmit and acknowledge ............. 78 capture/compare/pwm ........................................... 136 clkout and i/o ...................................................... 133 i 2 c bus data ............................................................ 140 i 2 c bus start/stop bits ............................................. 139 i 2 c master mode first start bit timing ........................ 69 i 2 c master mode reception timing ............................ 74 i 2 c master mode transmission timing ....................... 72 master mode transmit clock arbitration .................... 77 power-up timer ....................................................... 134 repeat start condition ............................................... 70 reset ........................................................................ 134 spi master mode ....................................................... 58 spi slave mode (cke = 1) ........................................ 59 spi slave mode timing (cke = 0) ............................ 59 start-up timer .......................................................... 134 stop condition receive or transmit .......................... 76 time-out sequence on power-up .................... 103, 104 timer0 ..................................................................... 135 timer1 ..................................................................... 135 wake-up from sleep via interrupt ......................... 109 watchdog timer ...................................................... 134 tmr0 ................................................................................. 11 tmr0 register ..................................................................... 9 tmr1cs bit ....................................................................... 41 tmr1h .............................................................................. 11 tmr1h register .................................................................. 9 tmr1l ............................................................................... 11 tmr1l register ................................................................... 9 tmr1on bit ....................................................................... 41 tmr2 ................................................................................. 11 tmr2 register ..................................................................... 9 tmr2on bit ....................................................................... 45 toutps0 bit ..................................................................... 45 toutps1 bit ..................................................................... 45 toutps2 bit ..................................................................... 45 toutps3 bit ..................................................................... 45 trisa ................................................................................ 11 trisa register .................................................................. 10 trisb ................................................................................ 11 trisb register .................................................................. 10 trisc ................................................................................ 11 trisc register .................................................................. 10 u ua ...................................................................................... 54 update address, ua .......................................................... 54 w wake-up from sleep ................................................ 95, 108 interrupts ......................................................... 101, 102 mclr reset ............................................................ 102 timing diagram ....................................................... 109 wdt reset .............................................................. 102 watchdog timer (wdt) ............................................. 95, 107 block diagram ......................................................... 107 enable (wdte bit) .................................................. 107 programming considerations .................................. 107 rc oscillator ........................................................... 107 time-out period ....................................................... 107 wdt reset, normal operation .................. 99, 101, 102 wdt reset, sleep .................................. 99, 101, 102 waveform for general call address sequence ................. 64 wcol .................................................. 55, 69, 71, 73, 75, 76 wcol status flag ............................................................. 69 write collision detect bit, wcol ....................................... 55 www, on-line support ...................................................... 3
pic16f872 ds30221a-page 156 ? 1999 microchip technology inc. notes:
? 1999 microchip technology inc. preliminary ds30221a-page 157 pic16f872 on-line support microchip provides on-line support on the microchip world wide web (www) site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape or microsoft explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available by using your favorite internet browser to attach to: www.microchip.com the file transfer site is available by using an ftp ser- vice to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: ? latest microchip press releases ? technical support section with frequently asked questions ? design tips ?device errata ? job postings ? microchip consultant program member listing ? links to other useful web sites related to microchip products ? conferences for products, development sys- tems, technical information and more ? listing of seminars and events systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive any currently available upgrade kits.the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-480-786-7302 for the rest of the world. trademarks: the microchip name, logo, pic, picmicro, picstart, picmaster, pro mate and mplab are registered trademarks of microchip technology incorpo- rated in the u.s.a. and other countries. flex rom and fuzzy lab are trademarks and sqtp is a service mark of microchip in the u.s.a. all other trademarks mentioned herein are the property of their respective companies. 981103
pic16f872 ds30221a-page 158 preliminary 1999 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 786-7578. please list the following information, and use this outline to provide us with your comments about this data sheet. 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this data sheet easy to follow? if not, why? 4. what additions to the data sheet do you think would enhance the structure and subject? 5. what deletions from the data sheet could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? 8. how would you improve our software, systems, and silicon products? to : technical publications manager re: reader response total pages sent from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds30221a pic16f872
? 1999 microchip technology inc. preliminary ds30221a-page 159 pic16f872 pic16f872 product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. s ales and support part no. - x /xx xxx pattern package temperature range device device pic16f872, pic16f872t;v dd range 4.0v to 5.5v pic16lf872, pic16lf872t;v dd range 2.0v to 5.5v f = cmos flash lf = low power cmos flash t = in tape and reel - soic, ssop, packages only. temperature range blank = 0 c to 70 c (commercial) i= -40 c to +85 c (industrial) package so = soic sp = skinny plastic dip ss = ssop pattern qtp, sqtp, code or special requirements (blank otherwise) examples: a) pic16f872-i/sp 301 = industrial temp., pdip package, 20mhz, normal v dd limits, qtp pat- tern #301. b) pic16f872-i/so = industrial temp., soic package, 20 mhz, normal v dd limits. c) pic16f872/p = industrial temp., pdip pack- age, 10mhz, normal v dd limits. d) pic16lf872-i/ss = industrial temp., ssop package, dc - 20mhz, extended v dd limits. data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 786-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products.
information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or oth e r intellectual property rights arising from such use or otherwise. use of microchips products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. the microchip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and other countries. all rights reserved. al l other trademarks mentioned herein are the property of their respective companies. ds30221a-page 160 ? 1999 microchip technology inc. all rights reserved. ? 1999 microchip technology incorporated. printed in the usa. 12/99 printed on recycled paper. americas corporate office microchip technology inc. 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-786-7200 fax: 480-786-7277 technical support: 480-786-7627 web address: http://www.microchip.com atlanta microchip technology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston microchip technology inc. 5 mount royal avenue marlborough, ma 01752 tel: 508-480-9990 fax: 508-480-8575 chicago microchip technology inc. 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas microchip technology inc. 4570 westgrove drive, suite 160 addison, tx 75248 tel: 972-818-7423 fax: 972-818-2924 dayton microchip technology inc. two prestige place, suite 150 miamisburg, oh 45342 tel: 937-291-1654 fax: 937-291-9175 detroit microchip technology inc. tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 los angeles microchip technology inc. 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 new york microchip technology inc. 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 631-273-5305 fax: 631-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 americas (continued) toronto microchip technology inc. 5925 airport road, suite 200 mississauga, ontario l4v 1w1, canada tel: 905-405-6279 fax: 905-405-6253 asia/pacific hong kong microchip asia pacific unit 2101, tower 2 metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2-401-1200 fax: 852-2-401-3431 beijing microchip technology, beijing unit 915, 6 chaoyangmen bei dajie dong erhuan road, dongcheng district new china hong kong manhattan building beijing 100027 prc tel: 86-10-85282100 fax: 86-10-85282104 india microchip technology inc. india liaison office no. 6, legacy, convent road bangalore 560 025, india tel: 91-80-229-0061 fax: 91-80-229-0062 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa 222-0033 japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea tel: 82-2-554-7200 fax: 82-2-558-5934 shanghai microchip technology rm 406 shanghai golden bridge bldg. 2077 yanan road west, hong qiao district shanghai, prc 200335 tel: 86-21-6275-5700 fax: 86 21-6275-5060 asia/pacific (continued) singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore 188980 tel: 65-334-8870 fax: 65-334-8850 taiwan, r.o.c microchip technology taiwan 10f-1c 207 tung hua north road ta i p e i , ta i wa n , ro c tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe united kingdom arizona microchip technology ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44 118 921 5858 fax: 44-118 921-5835 denmark microchip technology denmark aps regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45 4420 9895 fax: 45 4420 9910 france arizona microchip technology sarl parc dactivite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany arizona microchip technology gmbh gustav-heinemann-ring 125 d-81739 mnchen, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy arizona microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-039-65791-1 fax: 39-039-6899883 11/15/99 w orldwide s ales and s ervice microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the companys quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchips quality system for the design and manufacture of development systems is iso 9001 certified.

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